[WIP] Refactor for embedded-hal v1.0.0-alpha.6 (master)

Blocked on embedded-hal v1.0.0 release (rust-embedded/embedded-hal#177)

Signed-off-by: Moritz Scheuren <moritz.scheuren@systec-electronic.com>

Author: systec-ms

Cargo.toml

@@ -15,30 +15,30 @@ version = "0.6.0"
 features = ["stm32f746", "rt"]
 
 [dependencies]
-as-slice = "0.1.0"
+as-slice = "0.2.1"
 cortex-m = "0.7"
 cortex-m-rt = ">=0.6.15, <0.8"
 embedded-time = "0.12.0"
-nb = "0.1.2"
+nb = "1.0.0"
 rtcc = "0.2"
 stm32f7 = "0.14.0"
-micromath = "1.0.0"
+micromath = "2.0.0"
 synopsys-usb-otg = { version = "0.2.3", features = ["cortex-m"], optional = true }
 stm32-fmc = { version = "0.2.0", features = ["sdram"], optional = true }
 rand_core = "0.6"
-bxcan = ">=0.4,  <0.6"
+bxcan = "0.6.0"
 
 [dependencies.bare-metal]
-version = "0.2.4"
-features = ["const-fn"]
+version = "1.0.0"
 
 [dependencies.cast]
 default-features = false
-version = "0.2.2"
+version = "0.3.0"
 
 [dependencies.embedded-hal]
-features = ["unproven"]
-version = "0.2.3"
+#version = "1.0.0"
+git = "https://github.com/rust-embedded/embedded-hal"
+rev = "c7497ba"
 
 [dependencies.void]
 default-features = false
@@ -52,7 +52,7 @@ version = "0.4.1"
 cortex-m-semihosting = "0.3.3"
 panic-halt = "0.2.0"
 panic-semihosting = "0.5.2"
-embedded-graphics = "0.6.1"
+embedded-graphics = "0.7.1"
 usb-device = "0.2.5"
 usbd-serial = "0.1.0"
 

src/adc.rs

@@ -11,7 +11,7 @@ use crate::pac::{ADC1, ADC2, ADC3, ADC_COMMON};
 
 use cortex_m::asm::delay;
 
-use embedded_hal::adc::{Channel, OneShot};
+use embedded_hal::adc::nb::{Channel, OneShot};
 
 #[derive(Clone, Copy, Debug, PartialEq)]
 #[allow(non_camel_case_types)]
@@ -95,7 +95,7 @@ macro_rules! adc_pins {
             impl Channel<$ADC> for $pin {
                 type ID = u8;
 
-                fn channel() -> u8 { $chan }
+                fn channel(&self) -> u8 { $chan }
             }
         )+
     };
@@ -442,8 +442,8 @@ macro_rules! adc_hal {
         {
             type Error = ();
 
-            fn read(&mut self, _pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
-                let res = self.convert(PIN::channel());
+            fn read(&mut self, pin: &mut PIN) -> nb::Result<WORD, Self::Error> {
+                let res = self.convert(PIN::channel(pin));
                 Ok(res.into())
             }
         }

src/delay.rs

@@ -1,10 +1,9 @@
 //! Delays
 
-use cast::u32;
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
 
-use crate::hal::blocking::delay::{DelayMs, DelayUs};
+use crate::hal::delay::blocking::DelayUs;
 use crate::rcc::Clocks;
 
 /// System timer (SysTick) as a delay provider
@@ -27,26 +26,10 @@ impl Delay {
     }
 }
 
-impl DelayMs<u32> for Delay {
-    fn delay_ms(&mut self, ms: u32) {
-        self.delay_us(ms * 1_000);
-    }
-}
-
-impl DelayMs<u16> for Delay {
-    fn delay_ms(&mut self, ms: u16) {
-        self.delay_ms(u32(ms));
-    }
-}
-
-impl DelayMs<u8> for Delay {
-    fn delay_ms(&mut self, ms: u8) {
-        self.delay_ms(u32(ms));
-    }
-}
+impl DelayUs for Delay {
+    type Error = ();
 
-impl DelayUs<u32> for Delay {
-    fn delay_us(&mut self, us: u32) {
+    fn delay_us(&mut self, us: u32) -> Result<(), Self::Error> {
         // The SysTick Reload Value register supports values between 1 and 0x00FFFFFF.
         const MAX_RVR: u32 = 0x00FF_FFFF;
 
@@ -70,17 +53,6 @@ impl DelayUs<u32> for Delay {
 
             self.syst.disable_counter();
         }
-    }
-}
-
-impl DelayUs<u16> for Delay {
-    fn delay_us(&mut self, us: u16) {
-        self.delay_us(u32(us))
-    }
-}
-
-impl DelayUs<u8> for Delay {
-    fn delay_us(&mut self, us: u8) {
-        self.delay_us(u32(us))
+        Ok(())
     }
 }

src/gpio.rs

@@ -47,10 +47,10 @@
 use core::convert::Infallible;
 use core::marker::PhantomData;
 
-pub use embedded_hal::digital::v2::PinState;
-use embedded_hal::digital::v2::{
+use embedded_hal::digital::blocking::{
     InputPin, IoPin, OutputPin, StatefulOutputPin, ToggleableOutputPin,
 };
+pub use embedded_hal::digital::PinState;
 
 use crate::pac::{EXTI, SYSCFG};
 use crate::rcc::{Enable, APB2};
@@ -450,7 +450,7 @@ impl<MODE, const P: char, const N: u8> Pin<Output<MODE>, P, N> {
 
     #[inline(always)]
     pub fn toggle(&mut self) {
-        if self.is_set_low() {
+        if self.is_set_low().unwrap() {
             self.set_high()
         } else {
             self.set_low()

src/gpio/erased.rs

@@ -99,7 +99,7 @@ impl<MODE> ErasedPin<Output<MODE>> {
 
     #[inline(always)]
     pub fn toggle(&mut self) {
-        if self.is_set_low() {
+        if self.is_set_low().unwrap() {
             self.set_high()
         } else {
             self.set_low()

src/gpio/partially_erased.rs

@@ -80,7 +80,7 @@ impl<MODE, const P: char> PartiallyErasedPin<Output<MODE>, P> {
 
     #[inline(always)]
     pub fn toggle(&mut self) {
-        if self.is_set_low() {
+        if self.is_set_low().unwrap() {
             self.set_high()
         } else {
             self.set_low()

src/i2c.rs

@@ -10,33 +10,50 @@ use crate::gpio::gpioc::PC9;
 use crate::gpio::gpiof::{PF0, PF1};
 use crate::gpio::gpioh::{PH4, PH5, PH7, PH8};
 use crate::gpio::AlternateOD;
-use crate::hal::blocking::i2c::{Read, Write, WriteRead};
+use crate::hal::i2c::{
+    self,
+    blocking::{Read, Write, WriteRead},
+};
 use crate::pac::{DWT, I2C1, I2C2, I2C3};
 use crate::rcc::{Clocks, Enable, GetBusFreq, RccBus, Reset};
-use nb::Error::{Other, WouldBlock};
-use nb::{Error as NbError, Result as NbResult};
+use nb;
 
 use cast::u16;
 
 /// I2C error
 #[derive(Debug, Eq, PartialEq)]
 #[non_exhaustive]
 pub enum Error {
-    /// Bus error
+    /// Bus error occurred. e.g. A START or a STOP condition is detected and is not
+    /// located after a multiple of 9 SCL clock pulses.
     Bus,
-    /// Arbitration loss
-    Arbitration,
-    /// No ack received
-    Acknowledge,
-    /// Overrun/underrun
+    /// The arbitration was lost, e.g. electrical problems with the clock signal
+    ArbitrationLoss,
+    /// A bus operation was not acknowledged, e.g. due to the addressed device not
+    /// being available on the bus or the device not being ready to process requests
+    /// at the moment
+    NoAcknowledge(i2c::NoAcknowledgeSource),
+    /// The peripheral receive buffer was overrun
     Overrun,
-    /// Bus is busy
-    Busy,
+    /// Timeout
+    Timeout,
     // Pec, // SMBUS mode only
     // Timeout, // SMBUS mode only
     // Alert, // SMBUS mode only
 }
 
+impl i2c::Error for Error {
+    fn kind(&self) -> i2c::ErrorKind {
+        match *self {
+            Error::Bus => i2c::ErrorKind::Bus,
+            Error::ArbitrationLoss => i2c::ErrorKind::ArbitrationLoss,
+            Error::NoAcknowledge(s) => i2c::ErrorKind::NoAcknowledge(s),
+            Error::Overrun => i2c::ErrorKind::Overrun,
+            _ => i2c::ErrorKind::Other,
+        }
+    }
+}
+
 /// SPI mode. The user should make sure that the requested frequency can be
 /// generated considering the buses clocks.
 #[derive(Debug, PartialEq)]
@@ -354,20 +371,22 @@ macro_rules! check_status_flag {
 
         if isr.berr().bit_is_set() {
             $i2c.icr.write(|w| w.berrcf().set_bit());
-            Err(Other(Error::Bus))
+            Err(nb::Error::Other(Error::Bus))
         } else if isr.arlo().bit_is_set() {
             $i2c.icr.write(|w| w.arlocf().set_bit());
-            Err(Other(Error::Arbitration))
+            Err(nb::Error::Other(Error::ArbitrationLoss))
         } else if isr.nackf().bit_is_set() {
             $i2c.icr.write(|w| w.stopcf().set_bit().nackcf().set_bit());
-            Err(Other(Error::Acknowledge))
+            Err(nb::Error::Other(Error::NoAcknowledge(
+                i2c::NoAcknowledgeSource::Unknown,
+            )))
         } else if isr.ovr().bit_is_set() {
             $i2c.icr.write(|w| w.stopcf().set_bit().ovrcf().set_bit());
-            Err(Other(Error::Overrun))
+            Err(nb::Error::Other(Error::Overrun))
         } else if isr.$flag().$status() {
             Ok(())
         } else {
-            Err(WouldBlock)
+            Err(nb::Error::WouldBlock)
         }
     }};
 }
@@ -376,7 +395,7 @@ macro_rules! busy_wait {
     ($nb_expr:expr, $exit_cond:expr) => {{
         loop {
             let res = $nb_expr;
-            if res != Err(WouldBlock) {
+            if res != Err(nb::Error::WouldBlock) {
                 break res;
             }
             if $exit_cond {
@@ -397,6 +416,17 @@ macro_rules! busy_wait_cycles {
     }};
 }
 
+// Map non-blocking errors to blocking errors
+macro_rules! nbError_to_Error {
+    ($nb_expr:expr) => {{
+        match $nb_expr {
+            Ok(()) => {}
+            Err(nb::Error::WouldBlock) => return Err(Error::Timeout),
+            Err(nb::Error::Other(error)) => return Err(error),
+        };
+    }};
+}
+
 // Generate the same code for both I2Cs
 macro_rules! hal {
     ($($I2CX:ident: ($i2cX:ident),)+) => {
@@ -531,25 +561,19 @@ macro_rules! hal {
 
                 /// Wait for a byte to be read and return it (ie for RXNE flag
                 /// to be set)
-                fn wait_byte_read(&self) -> NbResult<u8, Error> {
+                fn wait_byte_read(&self) -> Result<u8, Error> {
                     // Wait until we have received something
-                    busy_wait_cycles!(
-                        check_status_flag!(self.nb.i2c, rxne, is_not_empty),
-                        self.data_timeout
-                    )?;
+                    nbError_to_Error!(busy_wait_cycles!(check_status_flag!(self.nb.i2c, rxne, is_not_empty), self.data_timeout));
 
                     Ok(self.nb.i2c.rxdr.read().rxdata().bits())
                 }
 
                 /// Wait the write data register to be empty  (ie for TXIS flag
                 /// to be set) and write the byte to it
-                fn wait_byte_write(&self, byte: u8) -> NbResult<(), Error> {
+                fn wait_byte_write(&self, byte: u8) -> Result<(), Error> {
                     // Wait until we are allowed to send data
                     // (START has been ACKed or last byte when through)
-                    busy_wait_cycles!(
-                        check_status_flag!(self.nb.i2c, txis, is_empty),
-                        self.data_timeout
-                    )?;
+                    nbError_to_Error!(busy_wait_cycles!(check_status_flag!(self.nb.i2c, txis, is_empty), self.data_timeout));
 
                     // Put byte on the wire
                     self.nb.i2c.txdr.write(|w| w.txdata().bits(byte));
@@ -564,7 +588,7 @@ macro_rules! hal {
             }
 
             impl<SCL, SDA> Write for BlockingI2c<$I2CX, SCL, SDA> {
-                type Error = NbError<Error>;
+                type Error = Error;
 
                 /// Write bytes to I2C. Currently, `bytes.len()` must be less or
                 /// equal than 255
@@ -592,7 +616,7 @@ macro_rules! hal {
             }
 
             impl<SCL, SDA> Read for BlockingI2c<$I2CX, SCL, SDA> {
-                type Error = NbError<Error>;
+                type Error = Error;
 
                 /// Reads enough bytes from slave with `address` to fill `buffer`
                 fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
@@ -620,7 +644,7 @@ macro_rules! hal {
             }
 
             impl<SCL, SDA> WriteRead for BlockingI2c<$I2CX, SCL, SDA> {
-                type Error = NbError<Error>;
+                type Error = Error;
 
                 fn write_read(
                     &mut self,
@@ -642,10 +666,7 @@ macro_rules! hal {
 
                     // Wait until the write finishes before beginning to read.
                     // busy_wait2!(self.nb.i2c, tc, is_complete);
-                    busy_wait_cycles!(
-                        check_status_flag!(self.nb.i2c, tc, is_complete),
-                        self.data_timeout
-                    )?;
+                    nbError_to_Error!(busy_wait_cycles!(check_status_flag!(self.nb.i2c, tc, is_complete), self.data_timeout));
 
                     // reSTART and prepare to receive bytes into `buffer`
                     self.nb.start(addr, buffer.len() as u8, true, true);