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2 parents aeba2b7 + 55f282a commit c983ec0Copy full SHA for c983ec0
examples/blinky_delay.rs
@@ -22,7 +22,7 @@ fn main() -> ! {
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let rcc = p.RCC.constrain();
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// Configure clock and freeze it
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- let clocks = rcc.cfgr.sysclk(216_000_000.Hz()).freeze();
+ let clocks = rcc.cfgr.sysclk(216.MHz()).freeze();
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// Get delay provider
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let mut delay = Delay::new(cp.SYST, clocks);
src/ltdc.rs
@@ -85,7 +85,7 @@ impl<T: 'static + SupportedWord> DisplayController<T> {
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// Get base clock and PLLM divisor
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let base_clk: u32;
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match &hse {
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- Some(hse) => base_clk = hse.freq,
+ Some(hse) => base_clk = hse.freq.0,
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// If no HSE is provided, we use the HSI clock at 16 MHz
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None => base_clk = 16_000_000,
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}
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