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Merge pull request #149 from systec-ms/update_cortex-m_dep
Cargo: cortex-m "0.7", cortex-m-rt ">=0.6.15, <0.8", stm32f7 "0.14.0"
2 parents faf3818 + cc2a4fa commit 9e3bc23

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5 files changed

+29
-47
lines changed

5 files changed

+29
-47
lines changed

‎Cargo.toml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,12 +16,12 @@ features = ["stm32f746", "rt"]
1616

1717
[dependencies]
1818
as-slice = "0.1.0"
19-
cortex-m = "0.6.0"
20-
cortex-m-rt = "0.6.8"
19+
cortex-m = "0.7"
20+
cortex-m-rt = ">=0.6.15, <0.8"
2121
embedded-time = "0.12.0"
2222
nb = "0.1.2"
2323
rtcc = "0.2"
24-
stm32f7 = "0.11.0"
24+
stm32f7 = "0.14.0"
2525
micromath = "1.0.0"
2626
synopsys-usb-otg = { version = "0.2.3", features = ["cortex-m"], optional = true }
2727
stm32-fmc = { version = "0.2.0", features = ["sdram"], optional = true }

‎src/ltdc.rs‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -148,25 +148,25 @@ impl<T: 'static + SupportedWord> DisplayController<T> {
148148
while rcc.cr.read().pllsairdy().is_not_ready() {}
149149

150150
// Configure LTDC Timing registers
151-
ltdc.sscr.write(|w| unsafe {
151+
ltdc.sscr.write(|w| {
152152
w.hsw()
153153
.bits((config.h_sync - 1) as u16)
154154
.vsh()
155155
.bits((config.v_sync - 1) as u16)
156156
});
157-
ltdc.bpcr.write(|w| unsafe {
157+
ltdc.bpcr.write(|w| {
158158
w.ahbp()
159159
.bits((config.h_sync + config.h_back_porch - 1) as u16)
160160
.avbp()
161161
.bits((config.v_sync + config.v_back_porch - 1) as u16)
162162
});
163-
ltdc.awcr.write(|w| unsafe {
163+
ltdc.awcr.write(|w| {
164164
w.aaw()
165165
.bits((config.h_sync + config.h_back_porch + config.active_width - 1) as u16)
166166
.aah()
167167
.bits((config.v_sync + config.v_back_porch + config.active_height - 1) as u16)
168168
});
169-
ltdc.twcr.write(|w| unsafe {
169+
ltdc.twcr.write(|w| {
170170
w.totalw()
171171
.bits(total_width as u16)
172172
.totalh()
@@ -234,21 +234,21 @@ impl<T: 'static + SupportedWord> DisplayController<T> {
234234
let h_win_start = self.config.h_sync + self.config.h_back_porch - 1;
235235
let v_win_start = self.config.v_sync + self.config.v_back_porch - 1;
236236

237-
_layer.whpcr.write(|w| unsafe {
237+
_layer.whpcr.write(|w| {
238238
w.whstpos()
239239
.bits(h_win_start + 1)
240240
.whsppos()
241241
.bits(h_win_start + width)
242242
});
243-
_layer.wvpcr.write(|w| unsafe {
243+
_layer.wvpcr.write(|w| {
244244
w.wvstpos()
245245
.bits(v_win_start + 1)
246246
.wvsppos()
247247
.bits(v_win_start + height)
248248
});
249249

250250
// Set pixel format
251-
_layer.pfcr.write(|w| unsafe {
251+
_layer.pfcr.write(|w| {
252252
w.pf().bits(match &pixel_format {
253253
PixelFormat::ARGB8888 => 0b000,
254254
// PixelFormat::RGB888 => 0b001,
@@ -263,7 +263,7 @@ impl<T: 'static + SupportedWord> DisplayController<T> {
263263
});
264264

265265
// Set global alpha value to 1 (255/255). Used for layer blending.
266-
_layer.cacr.write(|w| unsafe { w.consta().bits(0xFF) });
266+
_layer.cacr.write(|w| w.consta().bits(0xFF));
267267

268268
// Set default color to plain (not transparent) red (for debug
269269
// purposes). The default color is used outside the defined layer window
@@ -281,7 +281,7 @@ impl<T: 'static + SupportedWord> DisplayController<T> {
281281
// Color frame buffer start address
282282
_layer
283283
.cfbar
284-
.write(|w| unsafe { w.cfbadd().bits(buffer.as_ptr() as u32) });
284+
.write(|w| w.cfbadd().bits(buffer.as_ptr() as u32));
285285

286286
// Color frame buffer line length (active*byte per pixel + 3), and pitch
287287
let byte_per_pixel: u16 = match &pixel_format {
@@ -295,15 +295,15 @@ impl<T: 'static + SupportedWord> DisplayController<T> {
295295
PixelFormat::AL88 => 2,
296296
// _ => unimplemented!(),
297297
};
298-
_layer.cfblr.write(|w| unsafe {
298+
_layer.cfblr.write(|w| {
299299
w.cfbp()
300300
.bits(width * byte_per_pixel)
301301
.cfbll()
302302
.bits(width * byte_per_pixel + 3)
303303
});
304304

305305
// Frame buffer number of lines
306-
_layer.cfblnr.write(|w| unsafe { w.cfblnbr().bits(height) });
306+
_layer.cfblnr.write(|w| w.cfblnbr().bits(height));
307307

308308
// No Color Lookup table (CLUT)
309309
_layer.cr.modify(|_, w| w.cluten().clear_bit());

‎src/qspi.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ impl Qspi {
125125
)
126126
};
127127

128-
let rx_transfer = rx_transfer.start(&dma);
128+
let rx_transfer = rx_transfer.start(dma);
129129

130130
// Set DMA bit since we are using it
131131
self.qspi.cr.modify(|_, w| w.dmaen().set_bit());
@@ -174,7 +174,7 @@ impl Qspi {
174174
)
175175
};
176176

177-
let tx_transfer = tx_transfer.start(&dma);
177+
let tx_transfer = tx_transfer.start(dma);
178178

179179
// Set DMA bit since we are using it
180180
self.qspi.cr.modify(|_, w| w.dmaen().set_bit());

‎src/rcc.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1096,8 +1096,8 @@ bus! {
10961096
SPI5 => (APB2, spi5en, spi5rst),
10971097

10981098
USART1 => (APB2, usart1en, usart1rst),
1099-
USART2 => (APB1, usart2en, uart2rst),
1100-
USART3 => (APB1, usart3en, uart3rst),
1099+
USART2 => (APB1, usart2en, usart2rst),
1100+
USART3 => (APB1, usart3en, usart3rst),
11011101
UART4 => (APB1, uart4en, uart4rst),
11021102
UART5 => (APB1, uart5en, uart5rst),
11031103
USART6 => (APB2, usart6en, usart6rst),

‎src/rtc.rs‎

Lines changed: 11 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ impl Rtc {
6060
// Set 24 Hour
6161
regs.cr.modify(|_, w| w.fmt().clear_bit());
6262
// Set prescalers
63-
regs.prer.modify(|_, w| unsafe {
63+
regs.prer.modify(|_, w| {
6464
w.prediv_s().bits(prediv_s);
6565
w.prediv_a().bits(prediv_a)
6666
})
@@ -123,7 +123,7 @@ impl Rtcc for Rtc {
123123
let (mnt, mnu) = bcd2_encode(time.minute())?;
124124
let (st, su) = bcd2_encode(time.second())?;
125125
self.modify(|regs| {
126-
regs.tr.write(|w| unsafe {
126+
regs.tr.write(|w| {
127127
w.ht().bits(ht);
128128
w.hu().bits(hu);
129129
w.mnt().bits(mnt);
@@ -142,10 +142,7 @@ impl Rtcc for Rtc {
142142
return Err(Error::InvalidInputData);
143143
}
144144
let (st, su) = bcd2_encode(seconds as u32)?;
145-
self.modify(|regs| {
146-
regs.tr
147-
.modify(|_, w| unsafe { w.st().bits(st).su().bits(su) })
148-
});
145+
self.modify(|regs| regs.tr.modify(|_, w| w.st().bits(st).su().bits(su)));
149146

150147
Ok(())
151148
}
@@ -155,10 +152,7 @@ impl Rtcc for Rtc {
155152
return Err(Error::InvalidInputData);
156153
}
157154
let (mnt, mnu) = bcd2_encode(minutes as u32)?;
158-
self.modify(|regs| {
159-
regs.tr
160-
.modify(|_, w| unsafe { w.mnt().bits(mnt).mnu().bits(mnu) })
161-
});
155+
self.modify(|regs| regs.tr.modify(|_, w| w.mnt().bits(mnt).mnu().bits(mnu)));
162156

163157
Ok(())
164158
}
@@ -170,10 +164,7 @@ impl Rtcc for Rtc {
170164
Hours::AM(_h) | Hours::PM(_h) => self.set_12h_fmt(),
171165
}
172166

173-
self.modify(|regs| {
174-
regs.tr
175-
.modify(|_, w| unsafe { w.ht().bits(ht).hu().bits(hu) })
176-
});
167+
self.modify(|regs| regs.tr.modify(|_, w| w.ht().bits(ht).hu().bits(hu)));
177168

178169
Ok(())
179170
}
@@ -192,10 +183,7 @@ impl Rtcc for Rtc {
192183
return Err(Error::InvalidInputData);
193184
}
194185
let (dt, du) = bcd2_encode(day as u32)?;
195-
self.modify(|regs| {
196-
regs.dr
197-
.modify(|_, w| unsafe { w.dt().bits(dt).du().bits(du) })
198-
});
186+
self.modify(|regs| regs.dr.modify(|_, w| w.dt().bits(dt).du().bits(du)));
199187

200188
Ok(())
201189
}
@@ -205,10 +193,7 @@ impl Rtcc for Rtc {
205193
return Err(Error::InvalidInputData);
206194
}
207195
let (mt, mu) = bcd2_encode(month as u32)?;
208-
self.modify(|regs| {
209-
regs.dr
210-
.modify(|_, w| unsafe { w.mt().bit(mt > 0).mu().bits(mu) })
211-
});
196+
self.modify(|regs| regs.dr.modify(|_, w| w.mt().bit(mt > 0).mu().bits(mu)));
212197

213198
Ok(())
214199
}
@@ -218,10 +203,7 @@ impl Rtcc for Rtc {
218203
return Err(Error::InvalidInputData);
219204
}
220205
let (yt, yu) = bcd2_encode(year as u32 - 1970)?;
221-
self.modify(|regs| {
222-
regs.dr
223-
.modify(|_, w| unsafe { w.yt().bits(yt).yu().bits(yu) })
224-
});
206+
self.modify(|regs| regs.dr.modify(|_, w| w.yt().bits(yt).yu().bits(yu)));
225207

226208
Ok(())
227209
}
@@ -238,7 +220,7 @@ impl Rtcc for Rtc {
238220
let (dt, du) = bcd2_encode(date.day())?;
239221

240222
self.modify(|regs| {
241-
regs.dr.write(|w| unsafe {
223+
regs.dr.write(|w| {
242224
w.dt().bits(dt);
243225
w.du().bits(du);
244226
w.mt().bit(mt > 0);
@@ -266,15 +248,15 @@ impl Rtcc for Rtc {
266248
let (st, su) = bcd2_encode(date.second())?;
267249

268250
self.modify(|regs| {
269-
regs.dr.write(|w| unsafe {
251+
regs.dr.write(|w| {
270252
w.dt().bits(dt);
271253
w.du().bits(du);
272254
w.mt().bit(mt > 0);
273255
w.mu().bits(mu);
274256
w.yt().bits(yt);
275257
w.yu().bits(yu)
276258
});
277-
regs.tr.write(|w| unsafe {
259+
regs.tr.write(|w| {
278260
w.ht().bits(ht);
279261
w.hu().bits(hu);
280262
w.mnt().bits(mnt);

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