[WIP] Refactor for embedded-hal v1.0.0-alpha.6

Signed-off-by: Moritz Scheuren <moritz.scheuren@systec-electronic.com>

Author: systec-ms

Cargo.toml

@@ -15,30 +15,28 @@ version = "0.6.0"
 features = ["stm32f746", "rt"]
 
 [dependencies]
-as-slice = "0.1.0"
+as-slice = "0.2.1"
 cortex-m = "0.7"
 cortex-m-rt = ">=0.6.15, <0.8"
 embedded-time = "0.12.0"
-nb = "0.1.2"
+nb = "1.0.0"
 rtcc = "0.2"
 stm32f7 = "0.14.0"
-micromath = "1.0.0"
+micromath = "2.0.0"
 synopsys-usb-otg = { version = "0.2.3", features = ["cortex-m"], optional = true }
 stm32-fmc = { version = "0.2.0", features = ["sdram"], optional = true }
 rand_core = "0.6"
-bxcan = ">=0.4,  <0.6"
+bxcan = "0.6.2"
 
 [dependencies.bare-metal]
-version = "0.2.4"
-features = ["const-fn"]
+version = "1.0.0"
 
 [dependencies.cast]
 default-features = false
-version = "0.2.2"
+version = "0.3.0"
 
 [dependencies.embedded-hal]
-features = ["unproven"]
-version = "0.2.3"
+version = "1.0.0-alpha.6"
 
 [dependencies.void]
 default-features = false
@@ -52,7 +50,7 @@ version = "0.4.1"
 cortex-m-semihosting = "0.3.3"
 panic-halt = "0.2.0"
 panic-semihosting = "0.5.2"
-embedded-graphics = "0.6.1"
+embedded-graphics = "0.6.2"
 usb-device = "0.2.5"
 usbd-serial = "0.1.0"
 

examples/blinky_delay.rs

@@ -8,6 +8,7 @@
 extern crate panic_halt;
 
 use cortex_m_rt::entry;
+use embedded_hal::delay::blocking::DelayUs;
 use stm32f7xx_hal::{delay::Delay, pac, prelude::*};
 
 #[entry]
@@ -29,9 +30,9 @@ fn main() -> ! {
 
     loop {
         led.set_high();
-        delay.delay_ms(500_u16);
+        delay.delay_ms(500).unwrap();
 
         led.set_low();
-        delay.delay_ms(500_u16);
+        delay.delay_ms(500).unwrap();
     }
 }

examples/can-echo.rs

@@ -40,13 +40,13 @@ fn main() -> ! {
         let tx = gpioa.pa12.into_alternate();
 
         let can = Can::new(dp.CAN1, &mut rcc.apb1, (tx, rx));
-        bxcan::Can::new(can)
+
+        bxcan::Can::builder(can)
+            // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
+            // Value was calculated with http://www.bittiming.can-wiki.info/
+            .set_bit_timing(0x001e_000b)
+            .enable()
     };
-    can1.configure(|config| {
-        // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
-        // Value was calculated with http://www.bittiming.can-wiki.info/
-        config.set_bit_timing(0x001e_000b);
-    });
 
     // Configure filters so that can frames can be received.
     let mut filters = can1.modify_filters();
@@ -58,12 +58,11 @@ fn main() -> ! {
 
         let can = Can::new(dp.CAN2, &mut rcc.apb1, (tx, rx));
 
-        let mut can2 = bxcan::Can::new(can);
-        can2.configure(|config| {
+        let can2 = bxcan::Can::builder(can)
             // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
             // Value was calculated with http://www.bittiming.can-wiki.info/
-            config.set_bit_timing(0x001e_000b);
-        });
+            .set_bit_timing(0x001e_000b)
+            .enable();
 
         // A total of 28 filters are shared between the two CAN instances.
         // Split them equally between CAN1 and CAN2.
@@ -80,9 +79,6 @@ fn main() -> ! {
     let mut can = can1;
     //let mut can = can2;
 
-    // Split the peripheral into transmitter and receiver parts.
-    block!(can.enable()).unwrap();
-
     // Echo back received packages in sequence.
     // See the `can-rtfm` example for an echo implementation that adheres to
     // correct frame ordering based on the transfer id.

examples/can-loopback.rs

@@ -41,16 +41,14 @@ fn main() -> ! {
 
     let can = Can::new(dp.CAN1, &mut rcc.apb1, (tx, rx));
 
-    let mut can = bxcan::Can::new(can);
-
     // Use loopback mode: No pins need to be assigned to peripheral.
-    can.configure(|config| {
+    let mut can = bxcan::Can::builder(can)
         // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
         // Value was calculated with http://www.bittiming.can-wiki.info/
-        config.set_bit_timing(0x001e_000b);
-        config.set_loopback(true);
-        config.set_silent(true);
-    });
+        .set_bit_timing(0x001e_000b)
+        .set_loopback(true)
+        .set_silent(true)
+        .enable();
 
     let mut filters = can.modify_filters();
     assert!(filters.num_banks() > 3);
@@ -90,12 +88,9 @@ fn main() -> ! {
         ],
     );
 
-    // Enable filters.
+    // Drop filters to leave filter configuraiton mode.
     drop(filters);
 
-    // Sync to the bus and start normal operation.
-    block!(can.enable()).ok();
-
     // Some messages shall pass the filters.
     for &id in &[0, 1, 2, 8, 9, 10, 11] {
         let frame_tx = Frame::new_data(StandardId::new(id).unwrap(), [id as u8]);

examples/i2c_scanner.rs

@@ -11,6 +11,7 @@ use panic_semihosting as _;
 use cortex_m_rt::entry;
 use cortex_m_semihosting::{hprint, hprintln};
 
+use embedded_hal::i2c::blocking::Write;
 use stm32f7xx_hal::{self as hal, gpio::GpioExt, pac, prelude::*};
 
 const VALID_ADDR_RANGE: Range<u8> = 0x08..0x78;

examples/serial_delay.rs

@@ -12,6 +12,7 @@ extern crate panic_halt;
 use core::fmt::Write;
 
 use cortex_m_rt::entry;
+use embedded_hal::delay::blocking::DelayUs;
 use stm32f7xx_hal::{
     delay::Delay,
     pac,
@@ -50,6 +51,6 @@ fn main() -> ! {
     let hello: &str = "Hello, I'm a STM32F7xx!\r\n";
     loop {
         tx.write_str(hello).unwrap();
-        delay.delay_ms(500_u16);
+        delay.delay_ms(500).unwrap();
     }
 }

examples/serial_echo.rs

@@ -12,6 +12,7 @@ extern crate panic_halt;
 use nb::block;
 
 use cortex_m_rt::entry;
+use embedded_hal::serial::nb::{Read, Write};
 use stm32f7xx_hal::{
     pac,
     prelude::*,

examples/spi.rs

@@ -4,6 +4,7 @@
 extern crate panic_semihosting;
 
 use cortex_m_rt::entry;
+use embedded_hal::spi::blocking::TransferInplace;
 use stm32f7xx_hal::{
     pac,
     prelude::*,
@@ -48,7 +49,7 @@ fn main() -> ! {
         let mut buffer = [0; 2];
         buffer[0] = 0x75 | 0x80;
         ncs.set_low();
-        spi.transfer(&mut buffer).unwrap();
+        spi.transfer_inplace(&mut buffer).unwrap();
         ncs.set_high();
 
         // The WHO_AM_I register should always return 0x71.

examples/spi_16.rs

@@ -4,6 +4,7 @@
 extern crate panic_semihosting;
 
 use cortex_m_rt::entry;
+use embedded_hal::spi::blocking::Write;
 use stm32f7xx_hal::{
     pac,
     prelude::*,

examples/timer.rs

@@ -32,7 +32,7 @@ fn main() -> ! {
     unsafe {
         NVIC::unmask(pac::Interrupt::TIM2);
     }
-    let mut timer = Timer::tim2(dp.TIM2, 1.Hz(), clocks, &mut rcc.apb1);
+    let mut timer = Timer::tim2(dp.TIM2, 1.Hz(), clocks, &mut rcc.apb1).unwrap();
     timer.listen(Event::TimeOut);
 
     loop {}