Comments: Set PLLM, PLLN and PLLP

I have tested this code with a STM32f767 (at 216Mhz):

```rust
  let p = pac::Peripherals::take().unwrap();
  let rcc = p.RCC.constrain();
  let clocks = rcc
        .cfgr
        .hse(HSEClock {
            freq: 25_000_000,
            mode: HSEClockMode::Bypass,
        })
        .use_pll()
        .pllm(25)
        .plln(432)
        .pllp(PLLP::Div2)
        .sysclk(216_000_000.hz())
        .freeze();

```

Author: msmouni

src/rcc.rs

@@ -639,6 +639,8 @@ impl CFGR {
             return;
         }
 
+        /* We check if (pllm, plln, pllp) allow to obtain the requested Sysclk, 
+           so that we don't have to calculate them */
         let p_ok = (sysclk as u64)
             == (base_clk as u64 * self.plln as u64
                 / self.pllm as u64