Bumping package versions

Cryowatt · eldruin · commit 29ceb06c3745 · 2023-05-24T21:01:52.000+02:00
Rolled back dev-dependencies to previous versions to avoid breaking all of the examples
diff --git a/Cargo.toml b/Cargo.toml
@@ -21,10 +21,10 @@ as-slice = "0.2"
 cortex-m = "0.7.4"
 cortex-m-rt = ">=0.6.15, <0.8"
 nb = "1.0"
-stm32f7 = "0.14.0"
+stm32f7 = "0.15"
 micromath = "2.0"
-synopsys-usb-otg = { version = "0.2.3", features = ["cortex-m"], optional = true }
-stm32-fmc = { version = "0.2.0", features = ["sdram"], optional = true }
+synopsys-usb-otg = { version = "0.3", features = ["cortex-m"], optional = true }
+stm32-fmc = { version = "0.3", features = ["sdram"], optional = true }
 rand_core = "0.6"
 bxcan = "0.7"
 bare-metal = "1.0"
diff --git a/src/dma.rs b/src/dma.rs
@@ -741,22 +741,22 @@ pub trait SupportedWordSize: private::Sealed + Unpin + 'static {
 impl private::Sealed for u8 {}
 impl SupportedWordSize for u8 {
     fn msize() -> cr::MSIZE_A {
-        cr::MSIZE_A::BITS8
+        cr::MSIZE_A::Bits8
     }
 
     fn psize() -> cr::PSIZE_A {
-        cr::MSIZE_A::BITS8
+        cr::MSIZE_A::Bits8
     }
 }
 
 impl private::Sealed for u16 {}
 impl SupportedWordSize for u16 {
     fn msize() -> cr::MSIZE_A {
-        cr::MSIZE_A::BITS16
+        cr::MSIZE_A::Bits16
     }
 
     fn psize() -> cr::PSIZE_A {
-        cr::MSIZE_A::BITS16
+        cr::MSIZE_A::Bits16
     }
 }
 
diff --git a/src/rcc.rs b/src/rcc.rs
@@ -1277,33 +1277,33 @@ impl BusTimerClock for APB2 {
 impl From<MCO1> for crate::pac::rcc::cfgr::MCO1_A {
     fn from(input: MCO1) -> Self {
         match input {
-            MCO1::Hsi => Self::HSI,
-            MCO1::Lse => Self::LSE,
-            MCO1::Hse => Self::HSE,
-            MCO1::Pll => Self::PLL,
+            MCO1::Hsi => Self::Hsi,
+            MCO1::Lse => Self::Lse,
+            MCO1::Hse => Self::Hse,
+            MCO1::Pll => Self::Pll,
         }
     }
 }
 
 impl From<MCO2> for crate::pac::rcc::cfgr::MCO2_A {
     fn from(input: MCO2) -> Self {
         match input {
-            MCO2::Sysclk => Self::SYSCLK,
-            MCO2::Plli2s => Self::PLLI2S,
-            MCO2::Hse => Self::HSE,
-            MCO2::Pll => Self::PLL,
+            MCO2::Sysclk => Self::Sysclk,
+            MCO2::Plli2s => Self::Plli2s,
+            MCO2::Hse => Self::Hse,
+            MCO2::Pll => Self::Pll,
         }
     }
 }
 
 impl From<MCOPRE> for crate::pac::rcc::cfgr::MCO2PRE_A {
     fn from(input: MCOPRE) -> Self {
         match input {
-            MCOPRE::Div1_no_div => Self::DIV1,
-            MCOPRE::Div2 => Self::DIV2,
-            MCOPRE::Div3 => Self::DIV3,
-            MCOPRE::Div4 => Self::DIV4,
-            MCOPRE::Div5 => Self::DIV5,
+            MCOPRE::Div1_no_div => Self::Div1,
+            MCOPRE::Div2 => Self::Div2,
+            MCOPRE::Div3 => Self::Div3,
+            MCOPRE::Div4 => Self::Div4,
+            MCOPRE::Div5 => Self::Div5,
         }
     }
 }
diff --git a/src/spi.rs b/src/spi.rs
@@ -759,22 +759,22 @@ pub trait SupportedWordSize: dma::SupportedWordSize + private::Sealed {
 impl private::Sealed for u8 {}
 impl SupportedWordSize for u8 {
     fn frxth() -> cr2::FRXTH_A {
-        cr2::FRXTH_A::QUARTER
+        cr2::FRXTH_A::Quarter
     }
 
     fn ds() -> cr2::DS_A {
-        cr2::DS_A::EIGHTBIT
+        cr2::DS_A::EightBit
     }
 }
 
 impl private::Sealed for u16 {}
 impl SupportedWordSize for u16 {
     fn frxth() -> cr2::FRXTH_A {
-        cr2::FRXTH_A::HALF
+        cr2::FRXTH_A::Half
     }
 
     fn ds() -> cr2::DS_A {
-        cr2::DS_A::SIXTEENBIT
+        cr2::DS_A::SixteenBit
     }
 }
 
diff --git a/src/timer.rs b/src/timer.rs
@@ -376,7 +376,7 @@ macro_rules! with_pwm {
                 let tim = unsafe { &*<$TIM>::ptr() };
                 match channel {
                     0 => {
-                        tim.ccr1.read().bits()
+                        tim.ccr1().read().bits()
                     }
                     _ => 0,
                 }
@@ -388,7 +388,7 @@ macro_rules! with_pwm {
                 #[allow(unused_unsafe)]
                 match channel {
                     0 => {
-                        tim.ccr1.write(|w| unsafe { w.bits(value) })
+                        tim.ccr1().write(|w| unsafe { w.bits(value) })
                     }
                     _ => {},
                 }
@@ -433,10 +433,10 @@ macro_rules! with_pwm {
                 let tim = unsafe { &*<$TIM>::ptr() };
                 match channel {
                     0 => {
-                        tim.ccr1.read().bits()
+                        tim.ccr1().read().bits()
                     }
                     1 => {
-                        tim.ccr2.read().bits()
+                        tim.ccr2().read().bits()
                     }
                     _ => 0,
                 }
@@ -448,10 +448,10 @@ macro_rules! with_pwm {
                 #[allow(unused_unsafe)]
                 match channel {
                     0 => {
-                        tim.ccr1.write(|w| unsafe { w.bits(value) })
+                        tim.ccr1().write(|w| unsafe { w.bits(value) })
                     }
                     1 => {
-                        tim.ccr2.write(|w| unsafe { w.bits(value) })
+                        tim.ccr2().write(|w| unsafe { w.bits(value) })
                     }
                     _ => {},
                 }
@@ -500,16 +500,16 @@ macro_rules! with_pwm {
                 let tim = unsafe { &*<$TIM>::ptr() };
                 let ccr = match channel {
                     0 => {
-                        &tim.ccr1
+                        tim.ccr1()
                     }
                     1 => {
-                        &tim.ccr2
+                        tim.ccr2()
                     }
                     2 => {
-                        &tim.ccr3
+                        tim.ccr3()
                     }
                     _ => {
-                        &tim.ccr4
+                        tim.ccr4()
                     }
                 };
                 ccr.read().bits()
@@ -520,16 +520,16 @@ macro_rules! with_pwm {
                 let tim = unsafe { &*<$TIM>::ptr() };
                 let ccr = match channel {
                     0 => {
-                        &tim.ccr1
+                        tim.ccr1()
                     }
                     1 => {
-                        &tim.ccr2
+                        tim.ccr2()
                     }
                     2 => {
-                        &tim.ccr3
+                        tim.ccr3()
                     }
                     _ => {
-                        &tim.ccr4
+                        tim.ccr4()
                     }
                 };
                 ccr.write(|w| unsafe { w.bits(value) })
diff --git a/src/timer/pwm_input.rs b/src/timer/pwm_input.rs
@@ -182,11 +182,11 @@ macro_rules! hal {
         {
             /// Period of PWM signal in terms of clock cycles
             pub fn get_period_clocks(&self) -> <$TIM as General>::Width {
-                self.tim.ccr1.read().ccr().bits()
+                self.tim.ccr1().read().ccr().bits()
             }
             /// Duty cycle in terms of clock cycles
             pub fn get_duty_cycle_clocks(&self) -> <$TIM as General>::Width {
-                self.tim.ccr2.read().ccr().bits()
+                self.tim.ccr2().read().ccr().bits()
             }
             /// Observed duty cycle as a float in range [0.00, 1.00]
             pub fn get_duty_cycle(&self) -> f32 {

Original file line number	Diff line number	Diff line change
`@@ -741,22 +741,22 @@ pub trait SupportedWordSize: private::Sealed + Unpin + 'static {`
`741`	`741`	`impl private::Sealed for u8 {}`
`742`	`742`	`impl SupportedWordSize for u8 {`
`743`	`743`	`fn msize() -> cr::MSIZE_A {`
`744`		`- cr::MSIZE_A::BITS8`
	`744`	`+ cr::MSIZE_A::Bits8`
`745`	`745`	`}`
`746`	`746`
`747`	`747`	`fn psize() -> cr::PSIZE_A {`
`748`		`- cr::MSIZE_A::BITS8`
	`748`	`+ cr::MSIZE_A::Bits8`
`749`	`749`	`}`
`750`	`750`	`}`
`751`	`751`
`752`	`752`	`impl private::Sealed for u16 {}`
`753`	`753`	`impl SupportedWordSize for u16 {`
`754`	`754`	`fn msize() -> cr::MSIZE_A {`
`755`		`- cr::MSIZE_A::BITS16`
	`755`	`+ cr::MSIZE_A::Bits16`
`756`	`756`	`}`
`757`	`757`
`758`	`758`	`fn psize() -> cr::PSIZE_A {`
`759`		`- cr::MSIZE_A::BITS16`
	`759`	`+ cr::MSIZE_A::Bits16`
`760`	`760`	`}`
`761`	`761`	`}`
`762`	`762`
Original file line number	Diff line number	Diff line change
`@@ -1277,33 +1277,33 @@ impl BusTimerClock for APB2 {`
`1277`	`1277`	`impl From<MCO1> for crate::pac::rcc::cfgr::MCO1_A {`
`1278`	`1278`	`fn from(input: MCO1) -> Self {`
`1279`	`1279`	`match input {`
`1280`		`- MCO1::Hsi => Self::HSI,`
`1281`		`- MCO1::Lse => Self::LSE,`
`1282`		`- MCO1::Hse => Self::HSE,`
`1283`		`- MCO1::Pll => Self::PLL,`
	`1280`	`+ MCO1::Hsi => Self::Hsi,`
	`1281`	`+ MCO1::Lse => Self::Lse,`
	`1282`	`+ MCO1::Hse => Self::Hse,`
	`1283`	`+ MCO1::Pll => Self::Pll,`
`1284`	`1284`	`}`
`1285`	`1285`	`}`
`1286`	`1286`	`}`
`1287`	`1287`
`1288`	`1288`	`impl From<MCO2> for crate::pac::rcc::cfgr::MCO2_A {`
`1289`	`1289`	`fn from(input: MCO2) -> Self {`
`1290`	`1290`	`match input {`
`1291`		`- MCO2::Sysclk => Self::SYSCLK,`
`1292`		`- MCO2::Plli2s => Self::PLLI2S,`
`1293`		`- MCO2::Hse => Self::HSE,`
`1294`		`- MCO2::Pll => Self::PLL,`
	`1291`	`+ MCO2::Sysclk => Self::Sysclk,`
	`1292`	`+ MCO2::Plli2s => Self::Plli2s,`
	`1293`	`+ MCO2::Hse => Self::Hse,`
	`1294`	`+ MCO2::Pll => Self::Pll,`
`1295`	`1295`	`}`
`1296`	`1296`	`}`
`1297`	`1297`	`}`
`1298`	`1298`
`1299`	`1299`	`impl From<MCOPRE> for crate::pac::rcc::cfgr::MCO2PRE_A {`
`1300`	`1300`	`fn from(input: MCOPRE) -> Self {`
`1301`	`1301`	`match input {`
`1302`		`- MCOPRE::Div1_no_div => Self::DIV1,`
`1303`		`- MCOPRE::Div2 => Self::DIV2,`
`1304`		`- MCOPRE::Div3 => Self::DIV3,`
`1305`		`- MCOPRE::Div4 => Self::DIV4,`
`1306`		`- MCOPRE::Div5 => Self::DIV5,`
	`1302`	`+ MCOPRE::Div1_no_div => Self::Div1,`
	`1303`	`+ MCOPRE::Div2 => Self::Div2,`
	`1304`	`+ MCOPRE::Div3 => Self::Div3,`
	`1305`	`+ MCOPRE::Div4 => Self::Div4,`
	`1306`	`+ MCOPRE::Div5 => Self::Div5,`
`1307`	`1307`	`}`
`1308`	`1308`	`}`
`1309`	`1309`	`}`
Original file line number	Diff line number	Diff line change
`@@ -759,22 +759,22 @@ pub trait SupportedWordSize: dma::SupportedWordSize + private::Sealed {`
`759`	`759`	`impl private::Sealed for u8 {}`
`760`	`760`	`impl SupportedWordSize for u8 {`
`761`	`761`	`fn frxth() -> cr2::FRXTH_A {`
`762`		`- cr2::FRXTH_A::QUARTER`
	`762`	`+ cr2::FRXTH_A::Quarter`
`763`	`763`	`}`
`764`	`764`
`765`	`765`	`fn ds() -> cr2::DS_A {`
`766`		`- cr2::DS_A::EIGHTBIT`
	`766`	`+ cr2::DS_A::EightBit`
`767`	`767`	`}`
`768`	`768`	`}`
`769`	`769`
`770`	`770`	`impl private::Sealed for u16 {}`
`771`	`771`	`impl SupportedWordSize for u16 {`
`772`	`772`	`fn frxth() -> cr2::FRXTH_A {`
`773`		`- cr2::FRXTH_A::HALF`
	`773`	`+ cr2::FRXTH_A::Half`
`774`	`774`	`}`
`775`	`775`
`776`	`776`	`fn ds() -> cr2::DS_A {`
`777`		`- cr2::DS_A::SIXTEENBIT`
	`777`	`+ cr2::DS_A::SixteenBit`
`778`	`778`	`}`
`779`	`779`	`}`
`780`	`780`
Original file line number	Diff line number	Diff line change
`@@ -376,7 +376,7 @@ macro_rules! with_pwm {`
`376`	`376`	`let tim = unsafe { &*<$TIM>::ptr() };`
`377`	`377`	`match channel {`
`378`	`378`	`0 => {`
`379`		`- tim.ccr1.read().bits()`
	`379`	`+ tim.ccr1().read().bits()`
`380`	`380`	`}`
`381`	`381`	`_ => 0,`
`382`	`382`	`}`
`@@ -388,7 +388,7 @@ macro_rules! with_pwm {`
`388`	`388`	`#[allow(unused_unsafe)]`
`389`	`389`	`match channel {`
`390`	`390`	`0 => {`
`391`		`- tim.ccr1.write(\|w\| unsafe { w.bits(value) })`
	`391`	`+ tim.ccr1().write(\|w\| unsafe { w.bits(value) })`
`392`	`392`	`}`
`393`	`393`	`_ => {},`
`394`	`394`	`}`
`@@ -433,10 +433,10 @@ macro_rules! with_pwm {`
`433`	`433`	`let tim = unsafe { &*<$TIM>::ptr() };`
`434`	`434`	`match channel {`
`435`	`435`	`0 => {`
`436`		`- tim.ccr1.read().bits()`
	`436`	`+ tim.ccr1().read().bits()`
`437`	`437`	`}`
`438`	`438`	`1 => {`
`439`		`- tim.ccr2.read().bits()`
	`439`	`+ tim.ccr2().read().bits()`
`440`	`440`	`}`
`441`	`441`	`_ => 0,`
`442`	`442`	`}`
`@@ -448,10 +448,10 @@ macro_rules! with_pwm {`
`448`	`448`	`#[allow(unused_unsafe)]`
`449`	`449`	`match channel {`
`450`	`450`	`0 => {`
`451`		`- tim.ccr1.write(\|w\| unsafe { w.bits(value) })`
	`451`	`+ tim.ccr1().write(\|w\| unsafe { w.bits(value) })`
`452`	`452`	`}`
`453`	`453`	`1 => {`
`454`		`- tim.ccr2.write(\|w\| unsafe { w.bits(value) })`
	`454`	`+ tim.ccr2().write(\|w\| unsafe { w.bits(value) })`
`455`	`455`	`}`
`456`	`456`	`_ => {},`
`457`	`457`	`}`
`@@ -500,16 +500,16 @@ macro_rules! with_pwm {`
`500`	`500`	`let tim = unsafe { &*<$TIM>::ptr() };`
`501`	`501`	`let ccr = match channel {`
`502`	`502`	`0 => {`
`503`		`- &tim.ccr1`
	`503`	`+ tim.ccr1()`
`504`	`504`	`}`
`505`	`505`	`1 => {`
`506`		`- &tim.ccr2`
	`506`	`+ tim.ccr2()`
`507`	`507`	`}`
`508`	`508`	`2 => {`
`509`		`- &tim.ccr3`
	`509`	`+ tim.ccr3()`
`510`	`510`	`}`
`511`	`511`	`_ => {`
`512`		`- &tim.ccr4`
	`512`	`+ tim.ccr4()`
`513`	`513`	`}`
`514`	`514`	`};`
`515`	`515`	`ccr.read().bits()`
`@@ -520,16 +520,16 @@ macro_rules! with_pwm {`
`520`	`520`	`let tim = unsafe { &*<$TIM>::ptr() };`
`521`	`521`	`let ccr = match channel {`
`522`	`522`	`0 => {`
`523`		`- &tim.ccr1`
	`523`	`+ tim.ccr1()`
`524`	`524`	`}`
`525`	`525`	`1 => {`
`526`		`- &tim.ccr2`
	`526`	`+ tim.ccr2()`
`527`	`527`	`}`
`528`	`528`	`2 => {`
`529`		`- &tim.ccr3`
	`529`	`+ tim.ccr3()`
`530`	`530`	`}`
`531`	`531`	`_ => {`
`532`		`- &tim.ccr4`
	`532`	`+ tim.ccr4()`
`533`	`533`	`}`
`534`	`534`	`};`
`535`	`535`	`ccr.write(\|w\| unsafe { w.bits(value) })`
Original file line number	Diff line number	Diff line change
`@@ -182,11 +182,11 @@ macro_rules! hal {`
`182`	`182`	`{`
`183`	`183`	`/// Period of PWM signal in terms of clock cycles`
`184`	`184`	`pub fn get_period_clocks(&self) -> <$TIM as General>::Width {`
`185`		`- self.tim.ccr1.read().ccr().bits()`
	`185`	`+ self.tim.ccr1().read().ccr().bits()`
`186`	`186`	`}`
`187`	`187`	`/// Duty cycle in terms of clock cycles`
`188`	`188`	`pub fn get_duty_cycle_clocks(&self) -> <$TIM as General>::Width {`
`189`		`- self.tim.ccr2.read().ccr().bits()`
	`189`	`+ self.tim.ccr2().read().ccr().bits()`
`190`	`190`	`}`
`191`	`191`	`/// Observed duty cycle as a float in range [0.00, 1.00]`
`192`	`192`	`pub fn get_duty_cycle(&self) -> f32 {`