g4/f3/f0 init

Author: burrbull

.lapce/settings.toml

@@ -1,4 +1,4 @@
 [lapce-rust]
 check.allTargets = false
 check.targets = "thumbv7em-none-eabihf"
-cargo.features = ["rtic", "stm32f745"]
+cargo.features = ["rtic", "stm32l475"]

Cargo.toml

@@ -3,15 +3,18 @@
 use core::{
     convert::Infallible,
     marker::PhantomData,
-    ops::DerefMut,
-    sync::atomic::{self, Ordering},
+    //ops::DerefMut,
+    //sync::atomic::{self, Ordering},
 };
-
+#[cfg(feature = "dma")]
 use stable_deref_trait::StableDeref;
 
+#[cfg(feature = "dma")]
 use crate::{
     dma::{dma1, Event as DMAEvent, RxDma, Transfer, TransferPayload, W},
     dmamux::{DmaInput, DmaMux},
+};
+use crate::{
     gpio::{self, Analog},
     hal::{
         adc::{Channel as EmbeddedHalChannel, OneShot},
@@ -279,6 +282,7 @@ where
     }
 }
 
+#[cfg(feature = "dma")]
 impl TransferPayload for RxDma<Adc<ADC1>, dma1::C1> {
     fn start(&mut self) {
         self.channel.start();
@@ -289,13 +293,15 @@ impl TransferPayload for RxDma<Adc<ADC1>, dma1::C1> {
     }
 }
 
+#[cfg(feature = "dma")]
 impl RxDma<Adc<ADC1>, dma1::C1> {
     pub fn split(mut self) -> (Adc<ADC1>, dma1::C1) {
         self.stop();
         (self.payload, self.channel)
     }
 }
 
+#[cfg(feature = "dma")]
 impl<BUFFER, const N: usize> Transfer<W, BUFFER, RxDma<Adc<ADC1>, dma1::C1>>
 where
     BUFFER: Sized + StableDeref<Target = [u16; N]> + DerefMut + 'static,
@@ -675,15 +681,7 @@ macro_rules! adc {
                     delay: &mut impl DelayUs<u32>,
                 ) -> Self {
                     // Select system clock as ADC clock source
-                    ccipr.ccipr().modify(|_, w| {
-                        // This is sound, as `0b11` is a valid value for this field.
-                        unsafe {
-                            // TODO: Switch to enum once https://github.com/stm32-rs/stm32-rs/pull/720 is released.
-                            w.adcsel().bits(0b11);
-                        }
-
-                        w
-                    });
+                    ccipr.ccipr().modify(|_, w| w.adcsel().sysclk());
 
                     // Initialize the ADC, according to the STM32L4xx Reference Manual,
                     // section 16.4.6.

src/adc/l4.rs

@@ -293,22 +293,22 @@ pub use f3::*;
 mod f4;
 #[cfg(feature = "f4")]
 pub use f4::*;
-/*
+
 #[cfg(feature = "f7")]
 mod f7;
 #[cfg(feature = "f7")]
 pub use f7::*;
-
+/*
 #[cfg(feature = "g0")]
 mod g0;
 #[cfg(feature = "g0")]
 pub use g0::*;
-
+*/
 #[cfg(feature = "g4")]
 mod g4;
 #[cfg(feature = "g4")]
 pub use g4::*;
-
+/*
 #[cfg(feature = "h7")]
 mod h7;
 #[cfg(feature = "h7")]

src/dma/traits.rs

@@ -0,0 +1 @@
+

src/dma/traits/f7.rs

@@ -0,0 +1 @@
+

src/dma/traits/g4.rs

@@ -514,11 +514,11 @@ pub trait QuadSpiBanks {
 }
 #[cfg(feature = "quadspi")]
 pub trait QuadSpiBank {
-    type Io0;
-    type Io1;
-    type Io2;
-    type Io3;
-    type Ncs;
+    type Io0: crate::gpio::PinSpeed;
+    type Io1: crate::gpio::PinSpeed;
+    type Io2: crate::gpio::PinSpeed;
+    type Io3: crate::gpio::PinSpeed;
+    type Ncs: crate::gpio::PinSpeed;
 }
 
 // SAI pins

src/gpio/alt.rs

@@ -1,8 +1,5 @@
 use super::*;
-use crate::gpio::{self, Edge, ExtiPin};
-use crate::gpio::{marker, Alternate, NoPin, OpenDrain, PinMode, PushPull};
-use crate::pac::EXTI;
-use crate::syscfg::SysCfg;
+use crate::gpio::{self, NoPin, OpenDrain, PushPull};
 
 pub mod debug {
     use super::*;

src/gpio/alt/c0.rs

@@ -1,3 +1,6 @@
+use super::*;
+use crate::gpio::{self, NoPin, OpenDrain, PushPull};
+
 #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))]
 pub mod can {
     use super::*;

src/gpio/alt/f0.rs

@@ -1,8 +1,5 @@
 use super::*;
-use crate::gpio::{self, Edge, ExtiPin};
-use crate::gpio::{marker, Alternate, NoPin, OpenDrain, PinMode, PushPull};
-use crate::pac::EXTI;
-use crate::syscfg::SysCfg;
+use crate::gpio::{self, NoPin, OpenDrain, PushPull};
 
 pub mod can1 {
     use super::*;