Merge pull request #618 from stm32-rs/rcc-tim

enable_unchecked, timer features

Author: burrbull

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
  - Add autoimplementations of `DMASet` [#614]
  - Simplify `gpio::Outport` [#611]
+ - rcc `enable_unchecked`, timer features
  - Split SPI master and slave implementations [#609]
  - Split USART and UART implementations [#608]
  - Add `lapce` editor settings [#601]

Cargo.toml

@@ -121,22 +121,22 @@ gpio-f401 = [
     "otg-fs",
     "sdio",
     "spi3", "spi4",
-    "tim2",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim9", "tim10", "tim11",
 ]
 gpio-f410 = [
     "dac",
     "fmpi2c1",
     "lptim1",
     "spi5",
+    "tim1", "tim5", "tim6", "tim9", "tim11",
 ]
 gpio-f411 = [
     "gpiod", "gpioe", # "gpioi",
     "i2c3",
     "otg-fs",
     "sdio",
-    "tim2",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim9", "tim10", "tim11",
     "spi3", "spi4", "spi5",
-
 ]
 gpio-f412 = [
     "gpiod", "gpioe", "gpiof", "gpiog",
@@ -150,7 +150,7 @@ gpio-f412 = [
     "rng",
     "sdio",
     "spi3", "spi4", "spi5",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3",
 ]
 gpio-f413 = [
@@ -169,7 +169,7 @@ gpio-f413 = [
     "sai1",
     "sdio",
     "spi3", "spi4", "spi5",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5", "uart7", "uart8", "uart9", "uart10",
 ]
 gpio-f417 = [
@@ -186,7 +186,7 @@ gpio-f417 = [
     "rng",
     "sdio",
     "spi3",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5",
 ]
 gpio-f427 = [
@@ -204,7 +204,7 @@ gpio-f427 = [
     "sai1",
     "sdio",
     "spi3", "spi4", "spi5", "spi6",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5", "uart7", "uart8",
 ]
 gpio-f446 = [
@@ -224,7 +224,7 @@ gpio-f446 = [
     #"sdio",
     "spi3", "spi4",
     "spdifrx",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5",
 ]
 gpio-f469 = [
@@ -245,7 +245,7 @@ gpio-f469 = [
     "sai1",
     "sdio",
     "spi3", "spi4", "spi5", "spi6",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5", "uart7", "uart8",
 ]
 
@@ -296,8 +296,20 @@ spi4 = []
 spi5 = []
 spi6 = []
 spdifrx = []
+tim1 = []
 tim2 = []
+tim3 = []
+tim4 = []
+tim5 = []
+tim6 = []
+tim7 = []
 tim8 = []
+tim9 = []
+tim10 = []
+tim11 = []
+tim12 = []
+tim13 = []
+tim14 = []
 usart3 = []
 uart4 = []
 uart5 = []

src/can.rs

@@ -78,10 +78,8 @@ impl<CAN: Instance> Can<CAN> {
     /// Creates a CAN interface.
     pub fn new(can: CAN, pins: (impl Into<CAN::Tx>, impl Into<CAN::Rx>)) -> Self {
         unsafe {
-            // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-            let rcc = &(*crate::pac::RCC::ptr());
-            CAN::enable(rcc);
-            CAN::reset(rcc);
+            CAN::enable_unchecked();
+            CAN::reset_unchecked();
         }
 
         let pins = (pins.0.into(), pins.1.into());

src/crc32.rs

@@ -7,7 +7,7 @@
 //! It operates word-at-a-time, and takes 4 AHB/HCLK cycles per word
 //! to calculate. This operation stalls the AHB bus for that time.
 
-use crate::pac::{CRC, RCC};
+use crate::pac::CRC;
 use crate::rcc::{Enable, Reset};
 use core::mem::MaybeUninit;
 use core::ptr::copy_nonoverlapping;
@@ -21,11 +21,9 @@ impl Crc32 {
     /// Create a new Crc32 HAL peripheral
     pub fn new(crc: CRC) -> Self {
         unsafe {
-            // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-            let rcc = &(*RCC::ptr());
             // enable CRC clock.
-            CRC::enable(rcc);
-            CRC::reset(rcc);
+            CRC::enable_unchecked();
+            CRC::reset_unchecked();
         }
 
         let mut new = Self { periph: crc };
@@ -120,11 +118,9 @@ impl Crc32 {
 
     /// Consume the HAL peripheral, returning the PAC peripheral
     pub fn release(self) -> CRC {
+        // Disable CRC clock
         unsafe {
-            // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-            let rcc = &(*RCC::ptr());
-            // Disable CRC clock
-            CRC::disable(rcc);
+            CRC::disable_unchecked();
         }
 
         self.periph

src/dac.rs

@@ -6,7 +6,7 @@
 
 use crate::{
     gpio::{Analog, PA4, PA5},
-    pac::{DAC, RCC},
+    pac::DAC,
     rcc::{Enable, Reset},
 };
 
@@ -54,12 +54,9 @@ where
     PINS: Pins<DAC>,
 {
     unsafe {
-        // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-        let rcc = &(*RCC::ptr());
-
         // Enable and reset clock.
-        DAC::enable(rcc);
-        DAC::reset(rcc);
+        DAC::enable_unchecked();
+        DAC::reset_unchecked();
 
         PINS::init()
     }

src/dma/mod.rs

@@ -17,7 +17,6 @@ use core::{
 };
 use embedded_dma::{ReadBuffer, WriteBuffer};
 
-use crate::pac::RCC;
 use crate::{pac, rcc};
 
 pub mod traits;
@@ -267,10 +266,8 @@ impl<DMA: rcc::Enable + rcc::Reset> StreamsTuple<DMA> {
     /// Splits the DMA peripheral into streams.
     pub fn new(_regs: DMA) -> Self {
         unsafe {
-            //NOTE(unsafe) this reference will only be used for atomic writes with no side effects
-            let rcc = &(*RCC::ptr());
-            DMA::enable(rcc);
-            DMA::reset(rcc);
+            DMA::enable_unchecked();
+            DMA::reset_unchecked();
         }
         Self(
             StreamX::new(),

src/fsmc_lcd/mod.rs

@@ -68,7 +68,6 @@ use core::marker::PhantomData;
 pub use self::pins::{AddressPins, ChipSelectPins, DataPins, LcdPins, Pins};
 pub use self::timing::{AccessMode, Timing};
 
-use crate::pac::RCC;
 use crate::rcc::{Enable, Reset};
 
 // Use the FMC or FSMC, whichever is available, and treat it like an FSMC
@@ -204,11 +203,9 @@ where
     ) -> (Self, PINS::Lcds) {
         use self::sealed::Conjure;
         unsafe {
-            //NOTE(unsafe) this reference will only be used for atomic writes with no side effects
-            let rcc = &(*RCC::ptr());
             // Enable the FSMC/FMC peripheral
-            FSMC::enable(rcc);
-            FSMC::reset(rcc);
+            FSMC::enable_unchecked();
+            FSMC::reset_unchecked();
         }
 
         // Configure memory type and basic interface settings
@@ -238,13 +235,10 @@ where
     /// This function also resets and disables the FSMC.
     pub fn release(self, _lcds: PINS::Lcds) -> (FSMC, PINS) {
         unsafe {
-            //NOTE(unsafe) this reference will only be used for atomic writes with no side effects
-            let rcc = &(*RCC::ptr());
-            // All STM32F4 models with an FSMC or FMC use bit 0 in AHB3ENR and AHB3RSTR.
             // Reset FSMC/FMC
-            FSMC::reset(rcc);
+            FSMC::reset_unchecked();
             // Disable the FSMC/FMC peripheral
-            FSMC::disable(rcc);
+            FSMC::disable_unchecked();
         }
 
         (self.fsmc, self.pins)

src/gpio.rs

@@ -490,7 +490,7 @@ macro_rules! gpio {
     ]) => {
         /// GPIO
         pub mod $gpiox {
-            use crate::pac::{$GPIOX, RCC};
+            use crate::pac::$GPIOX;
             use crate::rcc::{Enable, Reset};
 
             /// GPIO parts
@@ -506,12 +506,9 @@ macro_rules! gpio {
 
                 fn split(self) -> Parts {
                     unsafe {
-                        // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-                        let rcc = &(*RCC::ptr());
-
                         // Enable clock.
-                        $GPIOX::enable(rcc);
-                        $GPIOX::reset(rcc);
+                        $GPIOX::enable_unchecked();
+                        $GPIOX::reset_unchecked();
                     }
                     Parts {
                         $(

src/i2c.rs

@@ -4,7 +4,6 @@ use crate::pac::{self, i2c1};
 use crate::rcc::{Enable, Reset};
 
 use crate::gpio;
-use crate::pac::RCC;
 
 use crate::rcc::Clocks;
 use embedded_hal_one::i2c::blocking::Operation;
@@ -162,12 +161,9 @@ where
         clocks: &Clocks,
     ) -> Self {
         unsafe {
-            // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-            let rcc = &(*RCC::ptr());
-
             // Enable and reset clock.
-            I2C::enable(rcc);
-            I2C::reset(rcc);
+            I2C::enable_unchecked();
+            I2C::reset_unchecked();
         }
 
         let pins = (pins.0.into(), pins.1.into());

src/i2s.rs

@@ -3,7 +3,7 @@
 //! This module is only available if the `i2s` feature is enabled.
 
 use crate::gpio::{self, NoPin};
-use crate::pac::{self, RCC};
+use crate::pac;
 use crate::rcc;
 use crate::rcc::Clocks;
 use fugit::HertzU32 as Hertz;
@@ -94,11 +94,9 @@ impl<SPI: Instance> I2s<SPI> {
     ) -> Self {
         let input_clock = SPI::i2s_freq(clocks);
         unsafe {
-            // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-            let rcc = &(*RCC::ptr());
             // Enable clock, enable reset, clear, reset
-            SPI::enable(rcc);
-            SPI::reset(rcc);
+            SPI::enable_unchecked();
+            SPI::reset_unchecked();
         }
 
         let pins = (pins.0.into(), pins.1.into(), pins.2.into(), pins.3.into());