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burrbullburrbull
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UART::steal & Deref
1 parent a79d290 commit 3185131

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7 files changed

+83
-144
lines changed

7 files changed

+83
-144
lines changed

‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1818

1919
- Use `stm32f4-staging` until `stm32f4` is released [#706]
2020
- Allow different lengths of buffers in hal_1 SpiBus impl [#566]
21+
- `steal` UART peripheral on `Rx::new`
2122

2223
[#566]: https://github.com/stm32-rs/stm32f4xx-hal/pull/566
2324
[#706]: https://github.com/stm32-rs/stm32f4xx-hal/pull/706

‎src/serial.rs‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,8 @@ pub struct Serial<USART: CommonPins, WORD = u8> {
183183

184184
/// Serial receiver containing RX pin
185185
pub struct Rx<USART: CommonPins, WORD = u8> {
186-
_word: PhantomData<(USART, WORD)>,
186+
_word: PhantomData<WORD>,
187+
usart: USART,
187188
pin: USART::Rx<PushPull>,
188189
}
189190

@@ -279,6 +280,10 @@ macro_rules! halUsart {
279280
fn peri_address() -> u32 {
280281
unsafe { (*(<$USART>::ptr() as *const Self::RegisterBlock)).peri_address() }
281282
}
283+
284+
unsafe fn steal() -> Self {
285+
Self::steal()
286+
}
282287
}
283288
};
284289
}
@@ -293,13 +298,13 @@ halUsart! { pac::USART3, Serial3, Rx3, Tx3 }
293298

294299
impl<UART: CommonPins> Rx<UART, u8> {
295300
pub(crate) fn with_u16_data(self) -> Rx<UART, u16> {
296-
Rx::new(self.pin)
301+
Rx::new(self.usart, self.pin)
297302
}
298303
}
299304

300305
impl<UART: CommonPins> Rx<UART, u16> {
301306
pub(crate) fn with_u8_data(self) -> Rx<UART, u8> {
302-
Rx::new(self.pin)
307+
Rx::new(self.usart, self.pin)
303308
}
304309
}
305310

@@ -316,9 +321,10 @@ impl<UART: CommonPins> Tx<UART, u16> {
316321
}
317322

318323
impl<UART: CommonPins, WORD> Rx<UART, WORD> {
319-
pub(crate) fn new(pin: UART::Rx<PushPull>) -> Self {
324+
pub(crate) fn new(usart: UART, pin: UART::Rx<PushPull>) -> Self {
320325
Self {
321326
_word: PhantomData,
327+
usart,
322328
pin,
323329
}
324330
}

‎src/serial/dma.rs‎

Lines changed: 9 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
use core::{marker::PhantomData, mem::transmute, ops::Deref};
1+
use core::{marker::PhantomData, mem::transmute};
22

33
use super::{Instance, RegisterBlockImpl, Serial};
44
use crate::dma::{
@@ -67,12 +67,7 @@ pub trait SerialHandleIT {
6767
fn handle_error_interrupt(&mut self);
6868
}
6969

70-
impl<Serial_> Serial<Serial_>
71-
where
72-
Serial_: Instance,
73-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
74-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
75-
{
70+
impl<Serial_: Instance> Serial<Serial_> {
7671
/// Converts blocking [Serial] to non-blocking [SerialDma] that use `tx_stream` and `rx_stream` to send/receive data
7772
pub fn use_dma<TX_STREAM, const TX_CH: u8, RX_STREAM, const RX_CH: u8>(
7873
self,
@@ -152,10 +147,7 @@ where
152147
///
153148
/// The struct can be also used to send/receive bytes in blocking mode with methods:
154149
/// [`write`](Self::write()), [`read`](Self::read()), [`write_read`](Self::write_read()).
155-
pub struct SerialDma<Serial_, TX_TRANSFER, RX_TRANSFER>
156-
where
157-
Serial_: Instance,
158-
{
150+
pub struct SerialDma<Serial_: Instance, TX_TRANSFER, RX_TRANSFER> {
159151
hal_serial: Serial<Serial_>,
160152
callback: Option<SerialCompleteCallback>,
161153
tx: TX_TRANSFER,
@@ -338,11 +330,8 @@ where
338330
}
339331

340332
/// Common implementation
341-
impl<Serial_, TX_TRANSFER, RX_TRANSFER> SerialDma<Serial_, TX_TRANSFER, RX_TRANSFER>
333+
impl<Serial_: Instance, TX_TRANSFER, RX_TRANSFER> SerialDma<Serial_, TX_TRANSFER, RX_TRANSFER>
342334
where
343-
Serial_: Instance,
344-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
345-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
346335
TX_TRANSFER: DMATransfer<&'static [u8]>,
347336
RX_TRANSFER: DMATransfer<&'static mut [u8]>,
348337
{
@@ -386,13 +375,9 @@ where
386375
}
387376
}
388377

389-
impl<Serial_, TX_STREAM, const TX_CH: u8> SerialHandleIT
378+
impl<Serial_: Instance, TX_STREAM, const TX_CH: u8> SerialHandleIT
390379
for SerialDma<Serial_, TxDMA<Serial_, TX_STREAM, TX_CH>, NoDMA>
391380
where
392-
Serial_: Instance,
393-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
394-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
395-
396381
TX_STREAM: Stream,
397382
ChannelX<TX_CH>: Channel,
398383
Tx<Serial_>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>,
@@ -428,13 +413,9 @@ where
428413
}
429414
}
430415

431-
impl<Serial_, RX_STREAM, const RX_CH: u8> SerialHandleIT
416+
impl<Serial_: Instance, RX_STREAM, const RX_CH: u8> SerialHandleIT
432417
for SerialDma<Serial_, NoDMA, RxDMA<Serial_, RX_STREAM, RX_CH>>
433418
where
434-
Serial_: Instance,
435-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
436-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
437-
438419
RX_STREAM: Stream,
439420
ChannelX<RX_CH>: Channel,
440421
Rx<Serial_>: DMASet<RX_STREAM, RX_CH, PeripheralToMemory>,
@@ -471,13 +452,9 @@ where
471452
}
472453

473454
/// Only for both TX and RX DMA
474-
impl<Serial_, TX_STREAM, const TX_CH: u8, RX_STREAM, const RX_CH: u8> SerialHandleIT
455+
impl<Serial_: Instance, TX_STREAM, const TX_CH: u8, RX_STREAM, const RX_CH: u8> SerialHandleIT
475456
for SerialDma<Serial_, TxDMA<Serial_, TX_STREAM, TX_CH>, RxDMA<Serial_, RX_STREAM, RX_CH>>
476457
where
477-
Serial_: Instance,
478-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
479-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
480-
481458
TX_STREAM: Stream,
482459
ChannelX<TX_CH>: Channel,
483460
Tx<Serial_>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>,
@@ -550,13 +527,9 @@ where
550527
}
551528

552529
// Write DMA implementations for TX only and TX/RX Serial DMA
553-
impl<Serial_, TX_STREAM, const TX_CH: u8, RX_TRANSFER> SerialWriteDMA
530+
impl<Serial_: Instance, TX_STREAM, const TX_CH: u8, RX_TRANSFER> SerialWriteDMA
554531
for SerialDma<Serial_, TxDMA<Serial_, TX_STREAM, TX_CH>, RX_TRANSFER>
555532
where
556-
Serial_: Instance,
557-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
558-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
559-
560533
TX_STREAM: Stream,
561534
ChannelX<TX_CH>: Channel,
562535
Tx<Serial_>: DMASet<TX_STREAM, TX_CH, MemoryToPeripheral>,
@@ -581,13 +554,9 @@ where
581554
}
582555

583556
// Read DMA implementations for RX only and TX/RX Serial DMA
584-
impl<Serial_, TX_TRANSFER, RX_STREAM, const RX_CH: u8> SerialReadDMA
557+
impl<Serial_: Instance, TX_TRANSFER, RX_STREAM, const RX_CH: u8> SerialReadDMA
585558
for SerialDma<Serial_, TX_TRANSFER, RxDMA<Serial_, RX_STREAM, RX_CH>>
586559
where
587-
Serial_: Instance,
588-
Serial_: Deref<Target = <Serial_ as Instance>::RegisterBlock>,
589-
<Serial_ as Instance>::RegisterBlock: RegisterBlockImpl,
590-
591560
RX_STREAM: Stream,
592561
ChannelX<RX_CH>: Channel,
593562
Rx<Serial_>: DMASet<RX_STREAM, RX_CH, PeripheralToMemory>,

‎src/serial/hal_02.rs‎

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
mod nb {
2-
use core::ops::Deref;
32

43
use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
54
use embedded_hal_02::serial::{Read, Write};
@@ -19,7 +18,7 @@ mod nb {
1918
type Error = Error;
2019

2120
fn read(&mut self) -> nb::Result<u8, Self::Error> {
22-
unsafe { (*USART::ptr()).read_u8() }
21+
self.usart.read_u8()
2322
}
2423
}
2524

@@ -32,7 +31,7 @@ mod nb {
3231
type Error = Error;
3332

3433
fn read(&mut self) -> nb::Result<u16, Self::Error> {
35-
unsafe { (*USART::ptr()).read_u16() }
34+
self.usart.read_u16()
3635
}
3736
}
3837

@@ -51,10 +50,7 @@ mod nb {
5150
}
5251
}
5352

54-
impl<USART: Instance> Write<u8> for Tx<USART, u8>
55-
where
56-
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
57-
{
53+
impl<USART: Instance> Write<u8> for Tx<USART, u8> {
5854
type Error = Error;
5955

6056
fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
@@ -70,10 +66,7 @@ mod nb {
7066
/// If the UART/USART was configured with `WordLength::DataBits9`, the 9 least significant bits will
7167
/// be transmitted and the other 7 bits will be ignored. Otherwise, the 8 least significant bits
7268
/// will be transmitted and the other 8 bits will be ignored.
73-
impl<USART: Instance> Write<u16> for Tx<USART, u16>
74-
where
75-
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
76-
{
69+
impl<USART: Instance> Write<u16> for Tx<USART, u16> {
7770
type Error = Error;
7871

7972
fn write(&mut self, word: u16) -> nb::Result<(), Self::Error> {
@@ -92,10 +85,7 @@ mod blocking {
9285
use super::super::{Error, Instance, RegisterBlockImpl, Serial, Tx};
9386
use embedded_hal_02::blocking::serial::Write;
9487

95-
impl<USART: Instance> Write<u8> for Tx<USART, u8>
96-
where
97-
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
98-
{
88+
impl<USART: Instance> Write<u8> for Tx<USART, u8> {
9989
type Error = Error;
10090

10191
fn bwrite_all(&mut self, bytes: &[u8]) -> Result<(), Self::Error> {

‎src/serial/hal_1.rs‎

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,4 @@
11
mod nb {
2-
use core::ops::Deref;
3-
42
use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
53
use embedded_hal_nb::serial::{ErrorKind, Read, Write};
64

@@ -37,7 +35,7 @@ mod nb {
3735

3836
impl<USART: Instance> Read<u8> for Rx<USART, u8> {
3937
fn read(&mut self) -> nb::Result<u8, Self::Error> {
40-
unsafe { (*USART::ptr()).read_u8() }
38+
self.usart.read_u8()
4139
}
4240
}
4341

@@ -48,7 +46,7 @@ mod nb {
4846
/// 8 received data bits and all other bits set to zero.
4947
impl<USART: Instance> Read<u16> for Rx<USART, u16> {
5048
fn read(&mut self) -> nb::Result<u16, Self::Error> {
51-
unsafe { (*USART::ptr()).read_u16() }
49+
self.usart.read_u16()
5250
}
5351
}
5452

@@ -65,10 +63,7 @@ mod nb {
6563
}
6664
}
6765

68-
impl<USART: Instance> Write<u8> for Tx<USART, u8>
69-
where
70-
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
71-
{
66+
impl<USART: Instance> Write<u8> for Tx<USART, u8> {
7267
fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
7368
self.usart.write_u8(word)
7469
}
@@ -82,10 +77,7 @@ mod nb {
8277
/// If the UART/USART was configured with `WordLength::DataBits9`, the 9 least significant bits will
8378
/// be transmitted and the other 7 bits will be ignored. Otherwise, the 8 least significant bits
8479
/// will be transmitted and the other 8 bits will be ignored.
85-
impl<USART: Instance> Write<u16> for Tx<USART, u16>
86-
where
87-
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
88-
{
80+
impl<USART: Instance> Write<u16> for Tx<USART, u16> {
8981
fn write(&mut self, word: u16) -> nb::Result<(), Self::Error> {
9082
self.usart.write_u16(word)
9183
}

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