Fix i2c_scanner example and use integer method for time types

Author: wbuck

CHANGELOG.md

@@ -11,7 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
-- Replace custom time based units with types defined in the [embedded-time][] crate ([#191])
+- Replace custom time based units with types defined in the [embedded-time][] crate ([#192])
 
 ### Breaking changes
 

examples/i2c_scanner.rs

@@ -38,7 +38,7 @@ fn main() -> ! {
     let mut i2c = hal::i2c::I2c::new(
         dp.I2C1,
         pins,
-        100_000u32.kHz().try_into().unwrap(),
+        100u32.kHz().try_into().unwrap(),
         clocks,
         &mut rcc.apb1,
     );

src/i2c.rs

@@ -12,7 +12,7 @@ use crate::{
     hal::blocking::i2c::{Read, Write, WriteRead},
     pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC},
     rcc::{Clocks, APB1},
-    time::rate::Hertz,
+    time::rate::*,
 };
 
 #[cfg(not(feature = "gpio-f333"))]
@@ -117,7 +117,7 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
         SCL: SclPin<I2C>,
         SDA: SdaPin<I2C>,
     {
-        crate::assert!(freq.0 <= 1_000_000);
+        crate::assert!(*freq.integer() <= 1_000_000);
 
         I2C::enable_clock(apb1);
 
@@ -130,16 +130,16 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
         // t_SYNC1 + t_SYNC2 > 4 * t_I2CCLK
         // t_SCL ~= t_SYNC1 + t_SYNC2 + t_SCLL + t_SCLH
         let i2cclk = I2C::clock(&clocks).0;
-        let ratio = i2cclk / freq.0 - 4;
-        let (presc, scll, sclh, sdadel, scldel) = if freq.0 >= 100_000 {
+        let ratio = i2cclk / *freq.integer() - 4;
+        let (presc, scll, sclh, sdadel, scldel) = if *freq.integer() >= 100_000 {
             // fast-mode or fast-mode plus
             // here we pick SCLL + 1 = 2 * (SCLH + 1)
             let presc = ratio / 387;
 
             let sclh = ((ratio / (presc + 1)) - 3) / 3;
             let scll = 2 * (sclh + 1) - 1;
 
-            let (sdadel, scldel) = if freq.0 > 400_000 {
+            let (sdadel, scldel) = if *freq.integer() > 400_000 {
                 // fast-mode plus
                 let sdadel = 0;
                 let scldel = i2cclk / 4_000_000 / (presc + 1) - 1;

src/pwm.rs

@@ -16,7 +16,7 @@
 
   ```
     // (Other imports omitted)
-    use stm32f3xx-hal::pwm::tim3;
+    use stm32f3xx-hal::{pwm::tim3, time::rate::*};
 
     let dp = stm32f303::Peripherals::take().unwrap();
 
@@ -25,9 +25,9 @@
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Set the resolution of our duty cycle to 9000 and our period to
-    // 50hz.
+    // 50Hz.
     let mut (c1_no_pins, _, _, c4_no_pins) =
-        tim3(device.TIM3, 9000, 50.hz(), clocks);
+        tim3(device.TIM3, 9000, 50.Hz(), clocks);
   ```
 
   In this case, we're only going to use channel 1 and channel 4.
@@ -65,7 +65,7 @@
     ch4.enable();
   ```
 
-  All three pins will output a 50hz period. PA6 and PB4 will share a
+  All three pins will output a 50Hz period. PA6 and PB4 will share a
   duty cycle, but the duty cycle for PB1 can be controlled
   independently.
 
@@ -84,7 +84,7 @@
 
   ```
     // (Other imports omitted)
-    use stm32f3xx-hal::pwm::tim16;
+    use stm32f3xx-hal::{pwm::tim16, time::rate::*};
 
     let dp = stm32f303::Peripherals::take().unwrap();
 
@@ -93,8 +93,8 @@
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Set the resolution of our duty cycle to 9000 and our period to
-    // 50hz.
-    let mut c1_no_pins = tim16(device.TIM3, 9000, 50.hz(), clocks);
+    // 50Hz.
+    let mut c1_no_pins = tim16(device.TIM3, 9000, 50.Hz(), clocks);
   ```
 
   ## Complementary timers
@@ -109,7 +109,7 @@
 
   ```
     // (Other imports omitted)
-    use stm32f3xx-hal::pwm::tim1;
+    use stm32f3xx-hal::{pwm::tim1, time::rate::*};
 
     let dp = stm32f303::Peripherals::take().unwrap();
 
@@ -118,8 +118,8 @@
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Set the resolution of our duty cycle to 9000 and our period to
-    // 50hz.
-    let mut (ch1_no_pins, _, _, _) = tim1(device.TIM3, 9000, 50.hz(), clocks);
+    // 50Hz.
+    let mut (ch1_no_pins, _, _, _) = tim1(device.TIM3, 9000, 50.Hz(), clocks);
 
     let mut gpioa = dp.GPIOB.split(&mut rcc.ahb);
     let pa7 = gpioa.pa7.into_af6(&mut gpioa.moder, &mut gpioa.afrl);
@@ -160,7 +160,7 @@ use crate::{
     hal::PwmPin,
     pac::{RCC, TIM15, TIM16, TIM17, TIM2},
     rcc::Clocks,
-    time::rate::Hertz,
+    time::rate::*,
 };
 use core::marker::PhantomData;
 
@@ -282,7 +282,7 @@ macro_rules! pwm_timer_private {
             // It might make sense to move into the clocks as a crate-only property.
             // TODO: ppre1 is used in timer.rs (never ppre2), should this be dynamic?
             let clock_freq = clocks.$pclkz().0 * if clocks.ppre1() == 1 { 1 } else { 2 };
-            let prescale_factor = clock_freq / res as u32 / freq.0;
+            let prescale_factor = clock_freq / res as u32 / *freq.integer();
             // NOTE(write): uses all bits of this register.
             tim.psc.write(|w| w.psc().bits(prescale_factor as u16 - 1));
 

src/rcc.rs

@@ -8,8 +8,7 @@
 //!
 //! ```
 //! # use cortex_m_rt::entry;
-//! # use stm32f3xx_hal::prelude::*;
-//! #use hal::time::rate::*;
+//! # use stm32f3xx-hal::{prelude::*, time::rate::*};
 //!
 //! # #[entry]
 //! # fn main() -> ! {
@@ -25,7 +24,8 @@
 //!
 //! ```
 //! # use cortex_m_rt::entry;
-//! # use stm32f3xx_hal::prelude::*;
+//! # use stm32f3xx-hal::{prelude::*, time::rate::*};
+//! #
 //! # #[entry]
 //! # fn main() -> ! {
 //! # let dp = pac::Peripherals::take().unwrap();
@@ -343,7 +343,7 @@ impl CFGR {
     /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`.
     pub fn use_hse(mut self, freq: Megahertz) -> Self {
         let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError");
-        self.hse = Some(freq.0);
+        self.hse = Some(*freq.integer());
         self
     }
 
@@ -376,7 +376,7 @@ impl CFGR {
     /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`.
     pub fn hclk(mut self, freq: Megahertz) -> Self {
         let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError");
-        self.hclk = Some(freq.0);
+        self.hclk = Some(*freq.integer());
         self
     }
 
@@ -392,7 +392,7 @@ impl CFGR {
     /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`.
     pub fn pclk1(mut self, freq: Megahertz) -> Self {
         let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError");
-        self.pclk1 = Some(freq.0);
+        self.pclk1 = Some(*freq.integer());
         self
     }
 
@@ -414,7 +414,7 @@ impl CFGR {
     /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`.
     pub fn pclk2(mut self, freq: Megahertz) -> Self {
         let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError");
-        self.pclk2 = Some(freq.0);
+        self.pclk2 = Some(*freq.integer());
         self
     }
 
@@ -439,7 +439,7 @@ impl CFGR {
     /// Panics if conversion from `Megahertz` to `Hertz` produces a value greater then `u32::MAX`.
     pub fn sysclk(mut self, freq: Megahertz) -> Self {
         let freq: Hertz = crate::expect!(freq.try_into(), "ConversionError");
-        self.sysclk = Some(freq.0);
+        self.sysclk = Some(*freq.integer());
         self
     }
 

src/serial.rs

@@ -5,7 +5,7 @@ use crate::{
     hal::{blocking, serial},
     pac::{USART1, USART2, USART3},
     rcc::{Clocks, APB1, APB2},
-    time::rate::Baud,
+    time::rate::*,
 };
 
 use cfg_if::cfg_if;
@@ -125,7 +125,7 @@ macro_rules! hal {
                     apb.rstr().modify(|_, w| w.$usartXrst().set_bit());
                     apb.rstr().modify(|_, w| w.$usartXrst().clear_bit());
 
-                    let brr = clocks.$pclkX().0 / baud_rate.0;
+                    let brr = clocks.$pclkX().0 / *baud_rate.integer();
                     crate::assert!(brr >= 16, "impossible baud rate");
                     // NOTE(write): uses all bits of this register.
                     usart.brr.write(|w| unsafe { w.bits(brr) });

src/spi.rs

@@ -131,7 +131,7 @@ use crate::rcc::APB1;
     feature = "stm32f398"
 ))]
 use crate::rcc::APB2;
-use crate::time::rate::Hertz;
+use crate::time::rate::*;
 use core::marker::PhantomData;
 
 /// SPI error
@@ -503,7 +503,7 @@ macro_rules! hal {
 
                 fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> spi1::cr1::BR_A {
                     use spi1::cr1::BR_A;
-                    match clocks.0 / freq.0 {
+                    match clocks.0 / *freq.integer() {
                         0 => crate::unreachable!(),
                         1..=2 => BR_A::DIV2,
                         3..=5 => BR_A::DIV4,

src/timer.rs

@@ -51,7 +51,7 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6};
 ))]
 use crate::pac::{TIM3, TIM7};
 use crate::rcc::{Clocks, APB1, APB2};
-use crate::time::rate::Hertz;
+use crate::time::rate::*;
 use void::Void;
 
 /// Associated clocks with timers
@@ -95,7 +95,7 @@ macro_rules! hal {
                 {
                     self.stop();
 
-                    let frequency = timeout.into().0;
+                    let frequency = *timeout.into().integer();
                     let timer_clock = $TIMX::get_clk(&self.clocks);
                     let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 }
                         / frequency;

src/watchdog.rs

@@ -7,7 +7,7 @@
 use crate::hal::watchdog::{Watchdog, WatchdogEnable};
 
 use crate::pac::{DBGMCU, IWDG};
-use crate::time::duration::Milliseconds;
+use crate::time::duration::*;
 
 const LSI_KHZ: u32 = 40;
 const MAX_PR: u8 = 8;
@@ -96,7 +96,7 @@ impl WatchdogEnable for IndependentWatchDog {
     type Time = Milliseconds;
 
     fn start<T: Into<Self::Time>>(&mut self, period: T) {
-        self.setup(period.into().0);
+        self.setup(*period.into().integer());
 
         self.iwdg.kr.write(|w| w.key().start());
     }