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[WIP] Add I2C slave.
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‎src/i2c_slave.rs‎

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use super::i2c::{SclPin, SdaPin};
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use super::pac::I2C1;
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#[derive(PartialEq)]
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pub enum TransferState {
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Idle,
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Addressed,
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RegisterSet,
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Receiving,
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Transmitting,
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}
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#[derive(Copy, Clone)]
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pub enum State {
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DataRequested(u8),
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DataReceived(u8),
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}
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const BUFFER_SIZE: usize = 32;
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pub struct I2CSlave<SDA, SCL> {
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i2c: I2C1,
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transfer_buffer: [u8; BUFFER_SIZE],
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transfer_len: usize,
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buffer_index: usize,
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register: u8,
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transfer_state: TransferState,
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state: Option<State>,
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_sda: SDA,
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_scl: SCL,
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}
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// direction as specified in the datasheet
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#[derive(PartialEq)]
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pub enum Direction {
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Write, // slave is receiver
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Read, // slave is transmitter
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}
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impl From<Direction> for bool {
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fn from(dir: Direction) -> Self {
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match dir {
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Direction::Write => false,
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Direction::Read => true,
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}
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}
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}
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impl From<bool> for Direction {
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fn from(raw: bool) -> Self {
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if raw {
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Direction::Read
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} else {
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Direction::Write
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}
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}
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}
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pub enum Status {
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AddressMatch(Direction),
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Busy,
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Timeout,
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Overrun,
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ArbitrationLost,
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BusError,
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TransferCompleteReload,
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Stop,
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NACKReceived,
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RxNotEmpty,
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TxDataMustBeWritten,
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TxEmpty,
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}
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impl<SDA, SCL> I2CSlave<SDA, SCL>
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where
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SDA: SdaPin<I2C1>,
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SCL: SclPin<I2C1>,
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{
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pub fn new(i2c: I2C1, address: u8, sda: SDA, scl: SCL) -> Self {
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let rcc = unsafe { &(*stm32f0xx_hal::pac::RCC::ptr()) };
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rcc.apb1enr.modify(|_, w| w.i2c1en().enabled());
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rcc.apb1rstr.modify(|_, w| w.i2c1rst().set_bit());
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rcc.apb1rstr.modify(|_, w| w.i2c1rst().clear_bit());
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i2c.cr1.write(|w| {
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w.nostretch()
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.enabled() // enable clock stretching
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.anfoff()
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.enabled() // enable analog filter
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.dnf()
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.no_filter() // disable digital filter
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.errie()
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.enabled() // error interrupt enabled
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.stopie()
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.enabled() // stop interrupt enabled
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.nackie()
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.enabled() // nack interrupt enabled
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.addrie()
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.enabled() // address match interrupt enabled
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.rxie() // rx interrupt enabled
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.enabled()
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.wupen()
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.enabled() // wake up when address match
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});
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// TODO set up timing for nostretch mode
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// let scll = cmp::max((((48_000_000 >> 1) >> 1) / KiloHertz(100).0) - 1, 255) as u8;
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// i2c.timingr.write(|w| {
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// w.presc()
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// .bits(1)
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// .scldel()
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// .bits(4)
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// .sdadel()
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// .bits(2)
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// .sclh()
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// .bits(scll - 4)
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// .scll()
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// .bits(scll)
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// });
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i2c.oar1.write(|w| {
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w.oa1en()
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.enabled()
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.oa1()
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.bits((address as u16) << 1)
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.oa1mode()
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.bit7()
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});
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i2c.cr1.modify(
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|_, w| w.pe().enabled(), // enable peripheral
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);
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I2CSlave {
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i2c,
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transfer_buffer: [0u8; BUFFER_SIZE],
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transfer_len: 0,
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buffer_index: 0,
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register: 0,
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transfer_state: TransferState::Idle,
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state: None,
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_sda: sda,
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_scl: scl,
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}
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}
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pub fn is_status(&self, status: Status, clear: bool) -> bool {
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let isr = self.i2c.isr.read();
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match status {
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Status::AddressMatch(dir) => {
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if isr.addr().bit_is_set() {
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if dir != isr.dir().bit().into() {
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return false;
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}
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if clear {
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self.i2c.icr.write(|w| w.addrcf().clear());
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}
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return true;
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} else {
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false
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}
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}
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Status::Busy => {
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return isr.busy().bit_is_set();
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}
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Status::Timeout => {
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if isr.timeout().bit_is_set() {
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if clear {
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self.i2c.icr.write(|w| w.timoutcf().clear());
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}
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return true;
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}
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return false;
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}
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Status::Overrun => {
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if isr.ovr().bit_is_set() {
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if clear {
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self.i2c.icr.write(|w| w.ovrcf().clear());
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}
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return true;
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}
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return false;
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}
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Status::ArbitrationLost => {
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if isr.arlo().bit_is_set() {
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if clear {
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self.i2c.icr.write(|w| w.arlocf().clear());
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}
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return true;
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}
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return false;
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}
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Status::BusError => {
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if isr.berr().bit_is_set() {
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if clear {
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self.i2c.icr.write(|w| w.berrcf().clear());
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}
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return true;
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}
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return false;
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}
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Status::TransferCompleteReload => {
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if isr.tcr().bit_is_set() {
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if clear {
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// defmt::error!("Cannot be cleared.");
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}
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return true;
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}
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return false;
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}
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Status::Stop => {
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if isr.stopf().bit_is_set() {
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if clear {
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self.i2c.icr.write(|w| w.stopcf().clear());
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}
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return true;
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}
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return false;
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}
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Status::NACKReceived => {
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if isr.nackf().bit_is_set() {
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if clear {
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self.i2c.icr.write(|w| w.nackcf().clear());
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}
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return true;
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}
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return false;
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}
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Status::RxNotEmpty => {
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if isr.rxne().bit_is_set() {
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if clear {
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// defmt::error!("Cannot be cleared.");
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}
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return true;
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}
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return false;
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}
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Status::TxDataMustBeWritten => {
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if isr.txis().bit_is_set() {
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if clear {
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// defmt::error!("Cannot be cleared.");
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}
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return true;
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}
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return false;
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}
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Status::TxEmpty => {
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if isr.txe().bit_is_set() {
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if clear {
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// defmt::error!("Cannot be cleared.");
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}
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return true;
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}
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return false;
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}
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}
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}
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pub fn read(&self) -> u8 {
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self.i2c.rxdr.read().bits() as u8
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}
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pub fn write(&self, value: u8) {
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self.i2c.txdr.write(|w| w.txdata().bits(value));
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}
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pub fn set_txe(&self) {
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self.i2c.isr.modify(|_, w| w.txe().set_bit());
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}
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pub fn enable_txie(&self, enable: bool) {
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self.i2c
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.cr1
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.modify(|_, w| w.txie().bit(enable).tcie().bit(enable));
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}
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pub fn interrupt(&mut self) {
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if self.transfer_state == TransferState::Idle {
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self.state = None;
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self.enable_txie(false);
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}
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if self.is_status(Status::BusError, true) {
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self.handle_error();
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return;
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}
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if self.is_status(Status::Overrun, true) {
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self.handle_error();
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return;
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}
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if self.is_status(Status::ArbitrationLost, true) {
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self.handle_error();
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return;
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}
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if self.is_status(Status::NACKReceived, true) {
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self.handle_error();
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return;
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}
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if self.is_status(Status::Timeout, true) {
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self.handle_error();
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return;
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}
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if self.is_status(Status::RxNotEmpty, false) {
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if self.transfer_state == TransferState::Addressed {
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self.transfer_state = TransferState::RegisterSet;
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self.register = self.read();
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} else if self.transfer_state == TransferState::RegisterSet {
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self.transfer_state = TransferState::Receiving;
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} else if self.transfer_state == TransferState::Receiving {
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// do not change state, just read
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self.transfer_buffer[self.buffer_index] = self.read();
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self.buffer_index += 1;
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}
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}
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if self.is_status(Status::Stop, true) {
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// handle reception
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if self.transfer_state == TransferState::Receiving {
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self.state = Some(State::DataReceived(self.register));
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} else if self.transfer_state == TransferState::Transmitting {
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// data was transmitted, nothing else to do
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self.state = None;
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}
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self.i2c.isr.modify(|_, w| w.txe().set_bit()); // flush txdr
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self.transfer_state = TransferState::Idle;
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}
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if self.is_status(Status::AddressMatch(Direction::Write), true) {
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self.transfer_state = TransferState::Addressed;
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}
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if self.is_status(Status::TxDataMustBeWritten, false) {
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// this may be true more times than actual data length, ignore then
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if self.transfer_state == TransferState::Transmitting {
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// state is not changed
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if self.buffer_index < self.transfer_len {
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self.write(self.transfer_buffer[self.buffer_index]);
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self.buffer_index += 1;
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} else {
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self.enable_txie(false);
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self.state = None;
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}
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}
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}
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if self.is_status(Status::AddressMatch(Direction::Read), true) {
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if self.transfer_state == TransferState::RegisterSet {
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self.enable_txie(true);
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self.transfer_state = TransferState::Transmitting;
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self.state = Some(State::DataRequested(self.register));
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}
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}
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}
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fn handle_error(&mut self) {
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self.transfer_state = TransferState::Idle;
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self.state = None;
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self.transfer_len = 0;
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self.buffer_index = 0;
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self.i2c.isr.modify(|_, w| w.txe().set_bit()); // flush txdr
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}
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pub fn set_transmit_buffer(&mut self, buffer: &[u8]) {
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for (index, item) in buffer.iter().enumerate() {
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self.transfer_buffer[index] = *item;
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}
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self.transfer_len = buffer.len();
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self.buffer_index = 0;
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self.state = None
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}
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pub fn get_received_data(&mut self) -> &[u8] {
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let data = &self.transfer_buffer[..self.buffer_index];
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self.state = None;
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self.buffer_index = 0;
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self.transfer_len = 0;
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data
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}
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pub fn get_state(&self) -> Option<State> {
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self.state
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}
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}

‎src/lib.rs‎

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@@ -44,6 +44,8 @@ pub mod gpio;
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#[cfg(feature = "device-selected")]
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pub mod i2c;
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#[cfg(feature = "device-selected")]
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pub mod i2c_slave;
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#[cfg(feature = "device-selected")]
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pub mod prelude;
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#[cfg(feature = "device-selected")]
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pub mod rcc;

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