Make f series compile again

Author: datdenkikniet

src/dma/mod.rs

@@ -6,12 +6,6 @@ use cortex_m::peripheral::NVIC;
 
 use crate::{peripherals::ETHERNET_DMA, stm32::Interrupt};
 
-#[cfg(feature = "f-series")]
-type ETHERNET_MTL = ();
-
-#[cfg(feature = "stm32h7xx-hal")]
-use crate::stm32::ETHERNET_MTL;
-
 #[cfg(feature = "smoltcp-phy")]
 mod smoltcp_phy;
 #[cfg(feature = "smoltcp-phy")]
@@ -77,7 +71,7 @@ pub struct EthernetDMA<'rx, 'tx> {
 pub(crate) struct DmaParts {
     pub eth_dma: ETHERNET_DMA,
     #[cfg(feature = "stm32h7xx-hal")]
-    pub eth_mtl: ETHERNET_MTL,
+    pub eth_mtl: crate::stm32::ETHERNET_MTL,
 }
 
 impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {

src/dma/rx/f_series_desc.rs

@@ -59,8 +59,7 @@ impl RxDescriptor {
     }
 
     pub(super) fn setup(&mut self, buffer: &mut [u8]) {
-        self.set_buffer(buffer);
-        self.set_owned();
+        self.set_owned(buffer);
     }
 
     /// Is owned by the DMA engine?
@@ -71,7 +70,9 @@ impl RxDescriptor {
     /// Pass ownership to the DMA engine
     ///
     /// Overrides old timestamp data
-    pub(super) fn set_owned(&mut self) {
+    pub(super) fn set_owned(&mut self, buffer: &mut [u8]) {
+        self.set_buffer(buffer);
+
         // "Preceding reads and writes cannot be moved past subsequent writes."
         #[cfg(feature = "fence")]
         atomic::fence(Ordering::Release);
@@ -125,11 +126,15 @@ impl RxDescriptor {
         ((self.inner_raw.read(0) >> RXDESC_0_FL_SHIFT) & RXDESC_0_FL_MASK) as usize
     }
 
-    pub(super) fn take_received(&mut self, packet_id: Option<PacketId>) -> Result<(), RxError> {
+    pub(super) fn take_received(
+        &mut self,
+        packet_id: Option<PacketId>,
+        buffer: &mut [u8],
+    ) -> Result<(), RxError> {
         if self.is_owned() {
             Err(RxError::WouldBlock)
         } else if self.has_error() {
-            self.set_owned();
+            self.set_owned(buffer);
             Err(RxError::DmaError)
         } else if self.is_first() && self.is_last() {
             // "Subsequent reads and writes cannot be moved ahead of preceding reads."
@@ -143,22 +148,22 @@ impl RxDescriptor {
 
             Ok(())
         } else {
-            self.set_owned();
+            self.set_owned(buffer);
             Err(RxError::Truncated)
         }
     }
 
     pub(super) fn set_end_of_ring(&mut self) {
         unsafe { self.inner_raw.modify(1, |w| w | RXDESC_1_RER) }
     }
+}
 
+#[cfg(feature = "ptp")]
+impl RxDescriptor {
     pub(super) fn packet_id(&self) -> Option<&PacketId> {
         self.packet_id.as_ref()
     }
-}
 
-#[cfg(feature = "ptp")]
-impl RxDescriptor {
     /// Get PTP timestamps if available
     pub(super) fn read_timestamp(&self) -> Option<Timestamp> {
         #[cfg(not(feature = "stm32f1xx-hal"))]

src/dma/rx/h_desc.rs

@@ -136,11 +136,12 @@ impl RxDescriptor {
     }
 
     pub(super) fn setup(&mut self, buffer: &[u8]) {
-        self.set_owned(buffer.as_ptr());
+        self.set_owned(buffer);
     }
 
     /// Pass ownership to the DMA engine
-    pub(super) fn set_owned(&mut self, buffer: *const u8) {
+    pub(super) fn set_owned(&mut self, buffer: &[u8]) {
+        let buffer = buffer.as_ptr();
         self.set_buffer(buffer);
 
         // "Preceding reads and writes cannot be moved past subsequent writes."
@@ -205,7 +206,7 @@ impl RxDescriptor {
 
             Ok(())
         } else {
-            self.set_owned(buffer.as_ptr());
+            self.set_owned(buffer);
             Err(RxError::Truncated)
         }
     }

src/dma/rx/mod.rs

@@ -280,7 +280,7 @@ impl<'a> core::ops::DerefMut for RxPacket<'a> {
 
 impl<'a> Drop for RxPacket<'a> {
     fn drop(&mut self) {
-        self.entry.set_owned(self.buffer.as_ptr());
+        self.entry.set_owned(self.buffer);
     }
 }
 

src/dma/tx/f_series_desc.rs

@@ -67,12 +67,6 @@ impl TxDescriptor {
 
     pub(super) fn setup(&mut self, buffer: &mut [u8]) {
         self.set_buffer(buffer);
-        unsafe {
-            self.inner_raw.write(
-                0,
-                TXDESC_0_CIC0 | TXDESC_0_CIC1 | TXDESC_0_FS | TXDESC_0_LS | TXDESC_0_IC,
-            );
-        }
     }
 
     #[allow(unused)]
@@ -112,7 +106,17 @@ impl TxDescriptor {
         atomic::fence(Ordering::Release);
         atomic::compiler_fence(Ordering::Release);
 
-        unsafe { self.inner_raw.modify(0, |w| w | extra_flags | TXDESC_0_OWN) };
+        unsafe {
+            self.inner_raw.modify(0, |w| {
+                w | extra_flags
+                    | TXDESC_0_OWN
+                    | TXDESC_0_CIC0
+                    | TXDESC_0_CIC1
+                    | TXDESC_0_FS
+                    | TXDESC_0_LS
+                    | TXDESC_0_IC
+            })
+        };
 
         // Used to flush the store buffer as fast as possible to make the buffer available for the
         // DMA.
@@ -144,14 +148,14 @@ impl TxDescriptor {
     pub(super) fn set_end_of_ring(&mut self) {
         unsafe { self.inner_raw.modify(0, |w| w | TXDESC_0_TER) };
     }
+}
 
+#[cfg(feature = "ptp")]
+impl TxDescriptor {
     pub(super) fn packet_id(&self) -> Option<&PacketId> {
         self.packet_id.as_ref()
     }
-}
 
-#[cfg(feature = "ptp")]
-impl TxDescriptor {
     fn read_timestamp(&mut self) -> Option<Timestamp> {
         let tdes0 = self.inner_raw.read(0);
 

src/dma/tx/mod.rs

@@ -41,7 +41,7 @@ pub(crate) struct TxRing<'data, STATE> {
 impl<'data, STATE> TxRing<'data, STATE> {
     pub fn running_state(&self, eth_dma: &ETHERNET_DMA) -> RunningState {
         #[cfg(feature = "f-series")]
-        let tx_status = eth_dma.dmasr().read().tps().bits();
+        let tx_status = eth_dma.dmasr.read().tps().bits();
 
         #[cfg(feature = "stm32h7xx-hal")]
         let tx_status = eth_dma.dmadsr.read().tps0().bits();
@@ -97,7 +97,7 @@ impl<'data> TxRing<'data, NotRunning> {
 
         #[cfg(feature = "f-series")]
         // Set end of ring register
-        self.ring.last_descriptor().set_end_of_ring();
+        self.ring.last_descriptor_mut().set_end_of_ring();
 
         let ring_ptr = self.ring.descriptors_start_address();
 
@@ -235,20 +235,20 @@ impl<'data> TxRing<'data, Running> {
 impl<'data> TxRing<'data, Running> {
     pub(crate) fn collect_timestamps(&mut self) {
         for descriptor in self.ring.descriptors_mut() {
-            f_descriptor.attach_timestamp();
+            descriptor.attach_timestamp();
         }
     }
 
     pub(crate) fn get_timestamp_for_id(&self, id: PacketId) -> Result<Timestamp, TimestampError> {
         let descriptor = if let Some(descriptor) =
             self.ring.descriptors().find(|d| d.packet_id() == Some(&id))
         {
-            f_descriptor
+            descriptor
         } else {
             return Err(TimestampError::IdNotFound);
         };
 
-        f_descriptor
+        descriptor
             .timestamp()
             .map(|t| *t)
             .ok_or(TimestampError::NotYetTimestamped)

src/lib.rs

@@ -108,32 +108,27 @@ where
     // Set up the clocks and reset the MAC periperhal
     setup::setup();
 
+    let dma_parts = DmaParts {
+        eth_dma: parts.dma.into(),
+        #[cfg(feature = "stm32h7xx-hal")]
+        eth_mtl: parts.mtl,
+    };
+
+    let mac_parts = MacParts {
+        eth_mac: parts.mac.into(),
+        #[cfg(feature = "f-series")]
+        eth_mmc: parts.mmc.into(),
+    };
+
     // Congfigure and start up the ethernet DMA.
-    let dma = EthernetDMA::new(
-        DmaParts {
-            eth_dma: parts.dma,
-            #[cfg(feature = "stm32h7xx-hal")]
-            eth_mtl: parts.mtl,
-        },
-        rx_buffer,
-        tx_buffer,
-    );
+    let dma = EthernetDMA::new(dma_parts, rx_buffer, tx_buffer);
 
     // Configure the ethernet PTP
     #[cfg(feature = "ptp")]
     let ptp = EthernetPTP::new(parts.ptp.into(), clocks, &dma);
 
     // Configure the ethernet MAC
-    let mac = EthernetMAC::new(
-        MacParts {
-            eth_mac: parts.mac.into(),
-            #[cfg(feature = "f-series")]
-            eth_mmc: parts.mmc.into(),
-        },
-        clocks,
-        Speed::FullDuplexBase100Tx,
-        &dma,
-    )?;
+    let mac = EthernetMAC::new(mac_parts, clocks, Speed::FullDuplexBase100Tx, &dma)?;
 
     let parts = Parts {
         mac,
@@ -192,23 +187,25 @@ where
     // Set up the clocks and reset the MAC periperhal
     setup::setup();
 
-    let eth_mac = parts.mac.into();
+    let dma_parts = DmaParts {
+        eth_dma: parts.dma.into(),
+    };
+
+    let mac_parts = MacParts {
+        eth_mac: parts.mac.into(),
+        eth_mmc: parts.mmc.into(),
+    };
 
     // Congfigure and start up the ethernet DMA.
-    let dma = EthernetDMA::new(parts.dma.into(), rx_buffer, tx_buffer);
+    let dma = EthernetDMA::new(dma_parts, rx_buffer, tx_buffer);
 
     // Configure the ethernet PTP
     #[cfg(feature = "ptp")]
     let ptp = EthernetPTP::new(parts.ptp.into(), clocks, &dma);
 
     // Configure the ethernet MAC
-    let mac = EthernetMAC::new(
-        MacParts { eth_mac, eth_mmc },
-        clocks,
-        Speed::FullDuplexBase100Tx,
-        &dma,
-    )?
-    .with_mii(mdio, mdc);
+    let mac =
+        EthernetMAC::new(mac_parts, clocks, Speed::FullDuplexBase100Tx, &dma)?.with_mii(mdio, mdc);
 
     let parts = Parts {
         mac,

src/mac/miim.rs

@@ -1,7 +1,8 @@
 pub use ieee802_3_miim::Miim;
-
 pub use ieee802_3_miim::*;
 
+use core::ops::{Deref, DerefMut};
+
 use crate::{peripherals::ETHERNET_MAC, stm32::ethernet_mac::MACMIIAR};
 
 use super::EthernetMAC;
@@ -157,7 +158,7 @@ where
     MDIO: MdioPin,
     MDC: MdcPin,
 {
-    pub(crate) eth_mac: EthernetMAC,
+    eth_mac: EthernetMAC,
     mdio: MDIO,
     mdc: MDC,
 }
@@ -226,7 +227,7 @@ where
     }
 }
 
-impl<MDIO, MDC> miim::Miim for EthernetMACWithMii<MDIO, MDC>
+impl<MDIO, MDC> Miim for EthernetMACWithMii<MDIO, MDC>
 where
     MDIO: MdioPin,
     MDC: MdcPin,