Examples

Author: datdenkikniet

build.rs

@@ -1,5 +1,4 @@
 fn main() {
-    #[cfg(feature = "stm32f1xx-hal")]
     println!("cargo:rustc-link-search=memory.x");
 
     let hse = std::env::var("STM32_ETH_EXAMPLE_HSE");

examples/arp.rs

@@ -23,7 +23,7 @@ use stm32_eth::{
 
 pub mod common;
 
-use stm32_eth::dma::{RxRingEntry, TxError, TxRingEntry};
+use stm32_eth::dma::TxError;
 
 const PHY_ADDR: u8 = 0;
 
@@ -43,22 +43,14 @@ fn main() -> ! {
 
     let (eth_pins, mdio, mdc, _) = common::setup_pins(gpio);
 
-    let mut rx_ring: [RxRingEntry; 2] = Default::default();
-    let mut tx_ring: [TxRingEntry; 2] = Default::default();
+    let (tx_ring, rx_ring) = crate::common::setup_rings();
 
     let Parts {
         mut dma,
         mac,
         #[cfg(feature = "ptp")]
             ptp: _,
-    } = stm32_eth::new(
-        ethernet,
-        &mut rx_ring[..],
-        &mut tx_ring[..],
-        clocks,
-        eth_pins,
-    )
-    .unwrap();
+    } = stm32_eth::new(ethernet, rx_ring, tx_ring, clocks, eth_pins).unwrap();
     dma.enable_interrupt();
 
     let mut last_link_up = false;
@@ -109,6 +101,8 @@ fn main() -> ! {
                 buf[38..42].copy_from_slice(&TARGET_IP);
             });
 
+            stm32_eth::eth_interrupt_handler();
+
             match r {
                 Ok(()) => {
                     defmt::info!("ARP sent");

examples/common.rs

@@ -5,14 +5,23 @@
 //!
 //! Note that this module isn't an example by itself.
 
+use core::mem::MaybeUninit;
+
 use defmt_rtt as _;
 use panic_probe as _;
 
 use stm32_eth::{
-    hal::{gpio::GpioExt, rcc::Clocks},
+    dma::{RxDescriptor, RxDescriptorRing, TxDescriptor, TxDescriptorRing, MTU},
+    hal::gpio::GpioExt,
     PartsIn,
 };
 
+#[cfg(feature = "f-series")]
+use stm32_eth::hal::rcc::Clocks;
+
+#[cfg(feature = "stm32h7xx-hal")]
+use stm32_eth::hal::rcc::CoreClocks as Clocks;
+
 pub use pins::{setup_pins, Gpio};
 
 use fugit::RateExtU32;
@@ -24,6 +33,33 @@ use stm32_eth::hal::rcc::RccExt;
 #[allow(unused)]
 fn main() {}
 
+const NUM_DESCRIPTORS: usize = 4;
+
+// On H7s, the ethernet DMA does not have access to the normal ram
+// so we must explicitly put them in SRAM.
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut TX_DESCRIPTORS: MaybeUninit<[TxDescriptor; NUM_DESCRIPTORS]> = MaybeUninit::uninit();
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut TX_BUFFERS: MaybeUninit<[[u8; MTU + 2]; NUM_DESCRIPTORS]> = MaybeUninit::uninit();
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut RX_DESCRIPTORS: MaybeUninit<[RxDescriptor; NUM_DESCRIPTORS]> = MaybeUninit::uninit();
+#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
+static mut RX_BUFFERS: MaybeUninit<[[u8; MTU + 2]; NUM_DESCRIPTORS]> = MaybeUninit::uninit();
+
+/// Set up the buffers to be used
+pub fn setup_rings() -> (TxDescriptorRing<'static>, RxDescriptorRing<'static>) {
+    let tx_desc = unsafe { TX_DESCRIPTORS.write([TxDescriptor::new(); NUM_DESCRIPTORS]) };
+    let tx_buf = unsafe { TX_BUFFERS.write([[0u8; MTU + 2]; NUM_DESCRIPTORS]) };
+
+    let rx_desc = unsafe { RX_DESCRIPTORS.write([RxDescriptor::new(); NUM_DESCRIPTORS]) };
+    let rx_buf = unsafe { RX_BUFFERS.write([[0u8; MTU + 2]; NUM_DESCRIPTORS]) };
+
+    (
+        TxDescriptorRing::new(tx_desc, tx_buf),
+        RxDescriptorRing::new(rx_desc, rx_buf),
+    )
+}
+
 /// Setup the clocks and return clocks and a GPIO struct that
 /// can be used to set up all of the pins.
 ///
@@ -33,8 +69,11 @@ pub fn setup_peripherals(p: stm32_eth::stm32::Peripherals) -> (Clocks, Gpio, Par
     let ethernet = PartsIn {
         dma: p.ETHERNET_DMA,
         mac: p.ETHERNET_MAC,
+        #[cfg(feature = "stm32h7xx-hal")]
+        mtl: p.ETHERNET_MTL,
+        #[cfg(feature = "f-series")]
         mmc: p.ETHERNET_MMC,
-        #[cfg(feature = "ptp")]
+        #[cfg(all(feature = "ptp", feature = "f-series"))]
         ptp: p.ETHERNET_PTP,
     };
 
@@ -109,6 +148,40 @@ pub fn setup_peripherals(p: stm32_eth::stm32::Peripherals) -> (Clocks, Gpio, Par
 
         (clocks, gpio, ethernet)
     }
+
+    #[cfg(feature = "stm32h7xx-hal")]
+    {
+        use stm32_eth::hal::pwr::PwrExt;
+
+        let rcc = p.RCC.constrain();
+        let pwr = p.PWR.constrain();
+
+        let syscfg = p.SYSCFG;
+
+        let pwrcfg = pwr.vos1().freeze();
+
+        let rcc = rcc.hclk(200.MHz()).sys_ck(200.MHz());
+
+        let rcc = if cfg!(hse = "bypass") {
+            rcc.bypass_hse().use_hse(8.MHz())
+        } else if cfg!(hse = "oscillator") {
+            rcc.use_hse(8.MHz())
+        } else {
+            rcc
+        };
+
+        let ccdr = rcc.freeze(pwrcfg, &syscfg);
+        let clocks = ccdr.clocks;
+
+        let gpio = Gpio {
+            gpioa: p.GPIOA.split(ccdr.peripheral.GPIOA),
+            gpiob: p.GPIOB.split(ccdr.peripheral.GPIOB),
+            gpioc: p.GPIOC.split(ccdr.peripheral.GPIOC),
+            gpiog: p.GPIOG.split(ccdr.peripheral.GPIOG),
+        };
+
+        (clocks, gpio, ethernet)
+    }
 }
 
 pub use pins::*;
@@ -290,6 +363,96 @@ mod pins {
     }
 }
 
+#[cfg(feature = "stm32h7xx-hal")]
+mod pins {
+    use stm32_eth::{
+        hal::gpio::{Input, PushPull, *},
+        EthPins,
+    };
+
+    pub struct Gpio {
+        pub gpioa: gpioa::Parts,
+        pub gpiob: gpiob::Parts,
+        pub gpioc: gpioc::Parts,
+        pub gpiog: gpiog::Parts,
+    }
+
+    pub type RefClk = PA1<Input>;
+    pub type Crs = PA7<Input>;
+
+    #[cfg(pins = "nucleo")]
+    pub type TxEn = PG11<Input>;
+    #[cfg(pins = "nucleo")]
+    pub type TxD0 = PG13<Input>;
+
+    #[cfg(not(pins = "nucleo"))]
+    pub type TxEn = PB11<Input>;
+    #[cfg(not(pins = "nucleo"))]
+    pub type TxD0 = PB12<Input>;
+
+    pub type TxD1 = PB13<Input>;
+    pub type RxD0 = PC4<Input>;
+    pub type RxD1 = PC5<Input>;
+
+    #[cfg(not(pps = "alternate"))]
+    pub type Pps = PB5<Output<PushPull>>;
+    #[cfg(pps = "alternate")]
+    pub type Pps = PG5<Output<PushPull>>;
+
+    pub type Mdio = PA2<Alternate<11>>;
+    pub type Mdc = PC1<Alternate<11>>;
+
+    pub fn setup_pins(
+        gpio: Gpio,
+    ) -> (
+        EthPins<RefClk, Crs, TxEn, TxD0, TxD1, RxD0, RxD1>,
+        Mdio,
+        Mdc,
+        Pps,
+    ) {
+        #[allow(unused_variables)]
+        let Gpio {
+            gpioa,
+            gpiob,
+            gpioc,
+            gpiog,
+        } = gpio;
+
+        let ref_clk = gpioa.pa1.into_input();
+        let crs = gpioa.pa7.into_input();
+        let rx_d0 = gpioc.pc4.into_input();
+        let rx_d1 = gpioc.pc5.into_input();
+        let tx_d1 = gpiob.pb13.into_input();
+
+        #[cfg(not(pins = "nucleo"))]
+        let (tx_en, tx_d0) = { (gpiob.pb11.into_input(), gpiob.pb12.into_input()) };
+
+        #[cfg(pins = "nucleo")]
+        let (tx_en, tx_d0) = { (gpiog.pg11.into_input(), gpiog.pg13.into_input()) };
+
+        let mdio = gpioa.pa2.into_alternate();
+        let mdc = gpioc.pc1.into_alternate();
+
+        #[cfg(not(pps = "alternate"))]
+        let pps = gpiob.pb5.into_push_pull_output();
+
+        #[cfg(pps = "alternate")]
+        let pps = gpiog.pg5.into_push_pull_output();
+
+        let pins = EthPins {
+            ref_clk,
+            crs,
+            tx_en,
+            tx_d0,
+            tx_d1,
+            rx_d0,
+            rx_d1,
+        };
+
+        (pins, mdio, mdc, pps)
+    }
+}
+
 use ieee802_3_miim::{
     phy::{
         lan87xxa::{LAN8720A, LAN8742A},

examples/rtic-echo.rs

@@ -26,11 +26,7 @@ mod app {
     use ieee802_3_miim::{phy::PhySpeed, Phy};
     use systick_monotonic::Systick;
 
-    use stm32_eth::{
-        dma::{EthernetDMA, RxRingEntry, TxRingEntry},
-        mac::Speed,
-        Parts,
-    };
+    use stm32_eth::{dma::EthernetDMA, mac::Speed, Parts};
 
     use smoltcp::{
         iface::{self, Interface, SocketHandle, SocketSet, SocketStorage},
@@ -58,8 +54,6 @@ mod app {
     }
 
     #[init(local = [
-        rx_ring: [RxRingEntry; 2] = [RxRingEntry::new(), RxRingEntry::new()],
-        tx_ring: [TxRingEntry; 2] = [TxRingEntry::new(), TxRingEntry::new()],
         rx_storage: [u8; 512] = [0u8; 512],
         tx_storage: [u8; 512] = [0u8; 512],
         socket_storage: [SocketStorage<'static>; 1] = [SocketStorage::EMPTY; 1],
@@ -69,8 +63,7 @@ mod app {
         let core = cx.core;
         let p = cx.device;
 
-        let rx_ring = cx.local.rx_ring;
-        let tx_ring = cx.local.tx_ring;
+        let (tx_ring, rx_ring) = crate::common::setup_rings();
 
         let (clocks, gpio, ethernet) = crate::common::setup_peripherals(p);
         let mono = Systick::new(core.SYST, clocks.hclk().raw());

memory.x

@@ -1,5 +1,63 @@
 MEMORY
 {
-  FLASH       : ORIGIN = 0x08000000, LENGTH = 128k
-  RAM         : ORIGIN = 0x20000000, LENGTH = 32K
+  /* FLASH and RAM are mandatory memory regions */
+
+  /* STM32H742xI/743xI/753xI       */
+  /* STM32H745xI/747xI/755xI/757xI */
+  /* STM32H7A3xI/7B3xI             */
+  FLASH  : ORIGIN = 0x08000000, LENGTH = 1M
+
+  /* STM32H742xG/743xG       */
+  /* STM32H745xG/STM32H747xG */
+  /* STM32H7A3xG             */
+  /* FLASH  : ORIGIN = 0x08000000, LENGTH = 512K */
+  /* FLASH1 : ORIGIN = 0x08100000, LENGTH = 512K */
+
+  /* STM32H750xB   */
+  /* STM32H7B0     */
+  /* FLASH  : ORIGIN = 0x08000000, LENGTH = 128K */
+
+  /* DTCM  */
+  RAM    : ORIGIN = 0x20000000, LENGTH = 128K
+
+  /* AXISRAM */
+  AXISRAM : ORIGIN = 0x24000000, LENGTH = 512K
+
+  /* SRAM */
+  SRAM1 : ORIGIN = 0x30000000, LENGTH = 128K
+  SRAM2 : ORIGIN = 0x30020000, LENGTH = 128K
+  /* SRAM3 : ORIGIN = 0x30040000, LENGTH = 32K */
+  SRAM4 : ORIGIN = 0x38000000, LENGTH = 64K
+
+  /* Backup SRAM */
+  BSRAM : ORIGIN = 0x38800000, LENGTH = 4K
+
+  /* Instruction TCM */
+  ITCM  : ORIGIN = 0x00000000, LENGTH = 64K
 }
+
+/* The location of the stack can be overridden using the
+   `_stack_start` symbol.  Place the stack at the end of RAM */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+
+/* The location of the .text section can be overridden using the
+   `_stext` symbol.  By default it will place after .vector_table */
+/* _stext = ORIGIN(FLASH) + 0x40c; */
+
+/* These sections are used for some of the examples */
+SECTIONS {
+  .axisram (NOLOAD) : ALIGN(8) {
+    *(.axisram .axisram.*);
+    . = ALIGN(8);
+    } > AXISRAM
+  /* The SRAM1 and SRAM2 section are commonly used as the stack and heap for the
+     CM4 core in dualcore versions and should thus not be used in examples*/
+  .sram4 (NOLOAD) : ALIGN(4) {
+    *(.sram4 .sram4.*);
+    . = ALIGN(4);
+    } > SRAM4
+  .sram1 (NOLOAD) : ALIGN(4) {
+    *(.sram1 .sram1.*);
+    . = ALIGN(4);
+  } > SRAM1
+};