@@ -293,7 +293,18 @@ ap3_err_t ap3_set_pin_to_analog(uint8_t pinNumber)
293293 uint8_t funcsel = 0 ;
294294 am_hal_gpio_pincfg_t pincfg = INPUT;
295295
296- retval = ap3_analog_pad_funcsel (ap3_gpio_pin2pad (pinNumber), &funcsel);
296+ // Handle special ADC channels
297+ if (pinNumber >= ADC_DIFF0 && pinNumber <= ADC_INTERNAL_VSS)
298+ {
299+ // Don't use the pin to pad lookup from the variant file
300+ retval = ap3_analog_pad_funcsel (pinNumber, &funcsel);
301+ }
302+ else
303+ {
304+ // Normal pin lookup
305+ retval = ap3_analog_pad_funcsel (ap3_gpio_pin2pad (pinNumber), &funcsel);
306+ }
307+
297308 if (retval != AP3_OK)
298309 {
299310 return retval;
@@ -355,15 +366,15 @@ ap3_err_t ap3_change_channel(uint8_t padNumber)
355366 return AP3_OK;
356367}
357368
358-
359- bool ap3_pwm_is_running ( uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) {
369+ bool ap3_pwm_is_running ( uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
370+ {
360371 volatile uint32_t *pui32ConfigReg;
361372 bool is_enabled = false ;
362373
363374 //
364375 // Find the correct control register.
365376 //
366- pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
377+ pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
367378
368379 //
369380 // Begin critical section while config registers are read and modified.
@@ -378,7 +389,8 @@ bool ap3_pwm_is_running(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
378389 //
379390 // Check the "enable bit"
380391 //
381- if ( ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk) ){
392+ if (ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk))
393+ {
382394 is_enabled = true ;
383395 }
384396
@@ -390,39 +402,51 @@ bool ap3_pwm_is_running(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
390402 return is_enabled;
391403}
392404
393-
394- void ap3_pwm_wait_for_pulse ( uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin) {
405+ void ap3_pwm_wait_for_pulse ( uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin)
406+ {
395407
396408 volatile uint32_t *pui32CompareReg;
397409 volatile uint32_t ctimer_val;
398410 uint32_t cmpr0;
399411
400412 // Only wait if the ctimer is running to avoid a deadlock
401- if ( ap3_pwm_is_running ( timer, segment) ){
413+ if (ap3_pwm_is_running (timer, segment))
414+ {
402415
403416 // Get the comapre register address
404- if ( segment == AM_HAL_CTIMER_TIMERA ){
405- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
406- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRA0);
407- }else {
408- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
417+ if (segment == AM_HAL_CTIMER_TIMERA)
418+ {
419+ if (output == AM_HAL_CTIMER_OUTPUT_NORMAL)
420+ {
421+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRA0);
422+ }
423+ else
424+ {
425+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
426+ }
427+ }
428+ else
429+ {
430+ if (output == AM_HAL_CTIMER_OUTPUT_NORMAL)
431+ {
432+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
409433 }
410- }else {
411- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
412- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
413- }else {
414- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
434+ else
435+ {
436+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
415437 }
416438 }
417439
418440 // Get the compare value
419441 cmpr0 = ((uint32_t )(*(pui32CompareReg)) & 0x0000FFFF );
420442
421- if ( cmpr0 ){ // Only wait when cmpr0 is greater than 0 to avoid an infinite while loop
443+ if (cmpr0)
444+ { // Only wait when cmpr0 is greater than 0 to avoid an infinite while loop
422445 // Wait for the timer value to be less than the compare value so that it is safe to change
423- ctimer_val = am_hal_ctimer_read ( timer, segment);
424- while ( (ctimer_val + 0 ) >= cmpr0 ){
425- ctimer_val = am_hal_ctimer_read ( timer, segment);
446+ ctimer_val = am_hal_ctimer_read (timer, segment);
447+ while ((ctimer_val + 0 ) >= cmpr0)
448+ {
449+ ctimer_val = am_hal_ctimer_read (timer, segment);
426450 }
427451 }
428452 }
@@ -534,16 +558,16 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
534558 if ((th == 0 ) || (fw == 0 ))
535559 {
536560 output = AM_HAL_CTIMER_OUTPUT_FORCE0;
537- set_periods = false ; // disable setting periods when going into a forced mode
561+ set_periods = false ; // disable setting periods when going into a forced mode
538562 }
539563 else if (th == fw)
540564 {
541565 output = AM_HAL_CTIMER_OUTPUT_FORCE1;
542- set_periods = false ; // disable setting periods when going into a forced mode
566+ set_periods = false ; // disable setting periods when going into a forced mode
543567 }
544568
545569 // Wait until after high pulse to change the state (avoids inversion)
546- ap3_pwm_wait_for_pulse ( timer, segment, output, 10 );
570+ ap3_pwm_wait_for_pulse (timer, segment, output, 10 );
547571
548572 // Configure the pin
549573 am_hal_ctimer_output_config (timer,
@@ -558,7 +582,8 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
558582 // (AM_HAL_CTIMER_FN_PWM_REPEAT | AP3_ANALOG_CLK | AM_HAL_CTIMER_INT_ENABLE) );
559583 (AM_HAL_CTIMER_FN_PWM_REPEAT | clk));
560584
561- if (set_periods){
585+ if (set_periods)
586+ {
562587 // If this pad uses secondary output:
563588 if (output == AM_HAL_CTIMER_OUTPUT_SECONDARY)
564589 {
@@ -603,17 +628,17 @@ ap3_err_t analogWriteResolution(uint8_t res)
603628ap3_err_t analogWrite (uint8_t pin, uint32_t val)
604629{
605630 // Determine the high time based on input value and the current resolution setting
606- uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
607- uint32_t fw = 0xFFFF ; // Choose the frame width in clock periods (32767 -> ~ 180 Hz)
631+ uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
632+ uint32_t fw = 0xFFFF ; // Choose the frame width in clock periods (32767 -> ~ 180 Hz)
608633 if (val >= ((0x01 << _analogWriteBits) - 1 ))
609634 {
610635 val = fw; // Enable FORCE1
611636 }
612637 else
613638 {
614- val <<= (16 - _analogWriteBits); // Shift over the value to fill available resolution
639+ val <<= (16 - _analogWriteBits); // Shift over the value to fill available resolution
615640 }
616-
641+
617642 return ap3_pwm_output (pin, val, fw, clk);
618643}
619644
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