@@ -129,7 +129,17 @@ uint16_t analogRead(uint8_t pinNumber)
129129 am_hal_adc_sample_t Sample;
130130 uint32_t ui32NumSamples = 1 ;
131131
132- uint8_t padNumber = ap3_gpio_pin2pad (pinNumber);
132+ uint8_t padNumber;
133+
134+ if (pinNumber >= ADC_DIFF0 && pinNumber <= ADC_INTERNAL_VSS)
135+ {
136+ // Special handling of internal ADC channels
137+ padNumber = pinNumber;
138+ }
139+ else
140+ {
141+ padNumber = ap3_gpio_pin2pad (pinNumber);
142+ }
133143
134144 // Look up configuration status based on pad number
135145 uint8_t indi;
@@ -292,8 +302,8 @@ ap3_err_t ap3_set_pin_to_analog(uint8_t pinNumber)
292302
293303 uint8_t funcsel = 0 ;
294304 am_hal_gpio_pincfg_t pincfg = INPUT;
295-
296305 retval = ap3_analog_pad_funcsel (ap3_gpio_pin2pad (pinNumber), &funcsel);
306+
297307 if (retval != AP3_OK)
298308 {
299309 return retval;
@@ -355,15 +365,15 @@ ap3_err_t ap3_change_channel(uint8_t padNumber)
355365 return AP3_OK;
356366}
357367
358-
359- bool ap3_pwm_is_running ( uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) {
368+ bool ap3_pwm_is_running ( uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
369+ {
360370 volatile uint32_t *pui32ConfigReg;
361371 bool is_enabled = false ;
362372
363373 //
364374 // Find the correct control register.
365375 //
366- pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
376+ pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
367377
368378 //
369379 // Begin critical section while config registers are read and modified.
@@ -378,7 +388,8 @@ bool ap3_pwm_is_running(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
378388 //
379389 // Check the "enable bit"
380390 //
381- if ( ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk) ){
391+ if (ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk))
392+ {
382393 is_enabled = true ;
383394 }
384395
@@ -390,39 +401,51 @@ bool ap3_pwm_is_running(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
390401 return is_enabled;
391402}
392403
393-
394- void ap3_pwm_wait_for_pulse ( uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin) {
404+ void ap3_pwm_wait_for_pulse ( uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin)
405+ {
395406
396407 volatile uint32_t *pui32CompareReg;
397408 volatile uint32_t ctimer_val;
398409 uint32_t cmpr0;
399410
400411 // Only wait if the ctimer is running to avoid a deadlock
401- if ( ap3_pwm_is_running ( timer, segment) ){
412+ if (ap3_pwm_is_running (timer, segment))
413+ {
402414
403415 // Get the comapre register address
404- if ( segment == AM_HAL_CTIMER_TIMERA ){
405- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ) {
406- pui32CompareReg = ( uint32_t *) CTIMERADDRn (CTIMER, timer, CMPRA0);
407- } else {
408- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXA0 );
416+ if ( segment == AM_HAL_CTIMER_TIMERA)
417+ {
418+ if (output == AM_HAL_CTIMER_OUTPUT_NORMAL)
419+ {
420+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRA0 );
409421 }
410- }else {
411- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
412- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
413- }else {
414- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
422+ else
423+ {
424+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
425+ }
426+ }
427+ else
428+ {
429+ if (output == AM_HAL_CTIMER_OUTPUT_NORMAL)
430+ {
431+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
432+ }
433+ else
434+ {
435+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
415436 }
416437 }
417438
418439 // Get the compare value
419440 cmpr0 = ((uint32_t )(*(pui32CompareReg)) & 0x0000FFFF );
420441
421- if ( cmpr0 ){ // Only wait when cmpr0 is greater than 0 to avoid an infinite while loop
442+ if (cmpr0)
443+ { // Only wait when cmpr0 is greater than 0 to avoid an infinite while loop
422444 // Wait for the timer value to be less than the compare value so that it is safe to change
423- ctimer_val = am_hal_ctimer_read ( timer, segment);
424- while ( (ctimer_val + 0 ) >= cmpr0 ){
425- ctimer_val = am_hal_ctimer_read ( timer, segment);
445+ ctimer_val = am_hal_ctimer_read (timer, segment);
446+ while ((ctimer_val + 0 ) >= cmpr0)
447+ {
448+ ctimer_val = am_hal_ctimer_read (timer, segment);
426449 }
427450 }
428451 }
@@ -534,16 +557,16 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
534557 if ((th == 0 ) || (fw == 0 ))
535558 {
536559 output = AM_HAL_CTIMER_OUTPUT_FORCE0;
537- set_periods = false ; // disable setting periods when going into a forced mode
560+ set_periods = false ; // disable setting periods when going into a forced mode
538561 }
539562 else if (th == fw)
540563 {
541564 output = AM_HAL_CTIMER_OUTPUT_FORCE1;
542- set_periods = false ; // disable setting periods when going into a forced mode
565+ set_periods = false ; // disable setting periods when going into a forced mode
543566 }
544567
545568 // Wait until after high pulse to change the state (avoids inversion)
546- ap3_pwm_wait_for_pulse ( timer, segment, output, 10 );
569+ ap3_pwm_wait_for_pulse (timer, segment, output, 10 );
547570
548571 // Configure the pin
549572 am_hal_ctimer_output_config (timer,
@@ -558,7 +581,8 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
558581 // (AM_HAL_CTIMER_FN_PWM_REPEAT | AP3_ANALOG_CLK | AM_HAL_CTIMER_INT_ENABLE) );
559582 (AM_HAL_CTIMER_FN_PWM_REPEAT | clk));
560583
561- if (set_periods){
584+ if (set_periods)
585+ {
562586 // If this pad uses secondary output:
563587 if (output == AM_HAL_CTIMER_OUTPUT_SECONDARY)
564588 {
@@ -603,17 +627,17 @@ ap3_err_t analogWriteResolution(uint8_t res)
603627ap3_err_t analogWrite (uint8_t pin, uint32_t val)
604628{
605629 // Determine the high time based on input value and the current resolution setting
606- uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
607- uint32_t fw = 0xFFFF ; // Choose the frame width in clock periods (32767 -> ~ 180 Hz)
630+ uint32_t clk = AM_HAL_CTIMER_HFRC_12MHZ; // Use an Ambiq HAL provided value to select which clock
631+ uint32_t fw = 0xFFFF ; // Choose the frame width in clock periods (32767 -> ~ 180 Hz)
608632 if (val >= ((0x01 << _analogWriteBits) - 1 ))
609633 {
610634 val = fw; // Enable FORCE1
611635 }
612636 else
613637 {
614- val <<= (16 - _analogWriteBits); // Shift over the value to fill available resolution
638+ val <<= (16 - _analogWriteBits); // Shift over the value to fill available resolution
615639 }
616-
640+
617641 return ap3_pwm_output (pin, val, fw, clk);
618642}
619643
0 commit comments