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1 | 1 | # reference: https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf |
2 | 2 | instr_set = { |
3 | | - # 21 |
4 | | - "j": { "OP": 0b000010, "FUNCT": "unlimited" }, |
5 | | - "jal": { "OP": 0b000011, "FUNCT": "unlimited" }, |
6 | | - "beq": { "OP": 0b000100, "FUNCT": "unlimited" }, |
7 | | - "bne": { "OP": 0b000101, "FUNCT": "unlimited" }, |
8 | | - "addi": { "OP": 0b001000, "FUNCT": "unlimited" }, |
9 | | - "addiu": { "OP": 0b001001, "FUNCT": "unlimited" }, |
10 | | - "slti": { "OP": 0b001010, "FUNCT": "unlimited" }, |
11 | | - "sltiu": { "OP": 0b001011, "FUNCT": "unlimited" }, |
12 | | - "andi": { "OP": 0b001100, "FUNCT": "unlimited" }, |
13 | | - "ori": { "OP": 0b001101, "FUNCT": "unlimited" }, |
14 | | - "xori": { "OP": 0b001110, "FUNCT": "unlimited" }, |
15 | | - "lui": { "OP": 0b001111, "RS": 0b00000, "FUNCT": "unlimited" }, |
| 3 | + # 2 |
| 4 | + "j": { "OP": 0b000010, "FUNCT": "unlimited" }, # J instr_index | J target |
| 5 | + "jal": { "OP": 0b000011, "FUNCT": "unlimited" }, # JAL instr_index | JAL target |
| 6 | + |
| 7 | + # 2 |
| 8 | + "beq": { "OP": 0b000100, "FUNCT": "unlimited" }, # BEQ rs rt immed | BEQ rs, rt, offset |
| 9 | + "bne": { "OP": 0b000101, "FUNCT": "unlimited" }, # BNE rs rt immed | BNE rs, rt, offset |
| 10 | + |
| 11 | + # 16 |
| 12 | + "addi": { "OP": 0b001000, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
| 13 | + "addiu": { "OP": 0b001001, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
| 14 | + "slti": { "OP": 0b001010, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
| 15 | + "sltiu": { "OP": 0b001011, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
| 16 | + "andi": { "OP": 0b001100, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
| 17 | + "ori": { "OP": 0b001101, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
| 18 | + "xori": { "OP": 0b001110, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, rs, offset |
16 | 19 | "clz": { "OP": 0b011100, "FUNCT": "unlimited" }, |
17 | | - "lb": { "OP": 0b100000, "FUNCT": "unlimited" }, |
18 | | - "lh": { "OP": 0b100001, "FUNCT": "unlimited" }, |
19 | | - "lw": { "OP": 0b100011, "FUNCT": "unlimited" }, |
20 | | - "lbu": { "OP": 0b100100, "FUNCT": "unlimited" }, |
21 | | - "lhu": { "OP": 0b100101, "FUNCT": "unlimited" }, |
22 | | - "sb": { "OP": 0b101000, "FUNCT": "unlimited" }, |
23 | | - "sh": { "OP": 0b101001, "FUNCT": "unlimited" }, |
24 | | - "sw": { "OP": 0b101011, "FUNCT": "unlimited" }, |
25 | | - |
26 | | - # 14 |
27 | | - "mul": { "OP": 0b011100, "SA": 0b00000, "FUNCT": 0b000010 }, |
28 | | - "sllv": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b000100 }, |
29 | | - "srlv": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b000110 }, |
30 | | - "srav": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b000111 }, |
31 | | - "add": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100000 }, |
32 | | - "addu": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100001 }, |
33 | | - "sub": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100010 }, |
34 | | - "subu": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100011 }, |
35 | | - "and": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100100 }, |
36 | | - "or": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100101 }, |
37 | | - "xor": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100110 }, |
38 | | - "nor": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100111 }, |
39 | | - "slt": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b101010 }, |
40 | | - "sltu": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b101011 }, |
| 20 | + "lb": { "OP": 0b100000, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 21 | + "lh": { "OP": 0b100001, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 22 | + "lw": { "OP": 0b100011, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 23 | + "lbu": { "OP": 0b100100, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 24 | + "lhu": { "OP": 0b100101, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 25 | + "sb": { "OP": 0b101000, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 26 | + "sh": { "OP": 0b101001, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 27 | + "sw": { "OP": 0b101011, "FUNCT": "unlimited" }, # OP rs rt immed | OP rt, offset(rs) |
| 28 | + |
| 29 | + # 1 |
| 30 | + "lui": { "OP": 0b001111, "RS": 0b00000, "FUNCT": "unlimited" }, # LUI 0 rt immed | LUI rt, offset |
| 31 | + |
| 32 | + # 1 |
| 33 | + "mul": { "OP": 0b011100, "SA": 0b00000, "FUNCT": 0b000010 }, # MUL rs rt rd 0 MUL | MUL rd, rs, rt |
| 34 | + |
| 35 | + # 13 |
| 36 | + "sllv": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b000100 }, # SPECIAL rs rt rd 0 SLLV | SLLV rd, rt, rs |
| 37 | + "srlv": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b000110 }, # SPECIAL rs rt rd 0 SRLV | SRLV rd, rt, rs |
| 38 | + "srav": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b000111 }, # SPECIAL rs rt rd 0 SRAV | SRAV rd, rt, rs |
| 39 | + "add": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100000 }, # SPECIAL rs rt rd 0 ADD | ADD rd, rs, rt |
| 40 | + "addu": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100001 }, # SPECIAL rs rt rd 0 ADDU | ADDU rd, rs, rt |
| 41 | + "sub": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100010 }, # SPECIAL rs rt rd 0 SUB | SUB rd, rs, rt |
| 42 | + "subu": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100011 }, # SPECIAL rs rt rd 0 SUBU | SUBU rd, rs, rt |
| 43 | + "and": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100100 }, # SPECIAL rs rt rd 0 AND | AND rd, rs, rt |
| 44 | + "or": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100101 }, # SPECIAL rs rt rd 0 OR | OR rd, rs, rt |
| 45 | + "xor": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100110 }, # SPECIAL rs rt rd 0 XOR | XOR rd, rs, rt |
| 46 | + "nor": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b100111 }, # SPECIAL rs rt rd 0 NOR | NOR rd, rs, rt |
| 47 | + "slt": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b101010 }, # SPECIAL rs rt rd 0 SLT | SLT rd, rs, rt |
| 48 | + "sltu": { "OP": 0b000000, "SA": 0b00000, "FUNCT": 0b101011 }, # SPECIAL rs rt rd 0 SLTU | SLTU rd, rs, rt |
41 | 49 |
|
42 | 50 | # 3 |
43 | | - "sll": { "OP": 0b000000, "RS": 0b00000, "FUNCT": 0b000000 }, |
44 | | - "srl": { "OP": 0b000000, "RS": 0b00000, "FUNCT": 0b000010 }, |
45 | | - "sra": { "OP": 0b000000, "RS": 0b00000, "FUNCT": 0b000011 }, |
| 51 | + "sll": { "OP": 0b000000, "RS": 0b00000, "FUNCT": 0b000000 }, # SPECIAL 0 rt, rd, sa, SLL | SLL rd, rt, sa |
| 52 | + "srl": { "OP": 0b000000, "RS": 0b00000, "FUNCT": 0b000010 }, # SPECIAL 0 rt, rd, sa, SRL | SRL rd, rt, sa |
| 53 | + "sra": { "OP": 0b000000, "RS": 0b00000, "FUNCT": 0b000011 }, # SPECIAL 0 rt, rd, sa, SRA | SRA rd, rt, sa |
46 | 54 |
|
47 | 55 | # 4 |
48 | | - "mult": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011000 }, |
49 | | - "multu": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011001 }, |
50 | | - "div": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011010 }, |
51 | | - "divu": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011011 }, |
| 56 | + "mult": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011000 }, # SPECIAL rs rt 10{0} MULTU | MULTU rs, rt |
| 57 | + "multu": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011001 }, # SPECIAL rs rt 10{0} MULTU | MULTU rs, rt |
| 58 | + "div": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011010 }, # SPECIAL rs rt 10{0} DIV | DIV rs, rt |
| 59 | + "divu": { "OP": 0b000000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011011 }, # SPECIAL rs rt 10{0} DIVU | DIVU rs, rt |
52 | 60 |
|
53 | | - # 3 |
54 | | - "syscall": { "OP": 0b000000, "FUNCT": 0b001100 }, |
| 61 | + # 2 |
| 62 | + "syscall": { "OP": 0b000000, "FUNCT": 0b001100 }, # SPECIAL code SYSCALL | SYSCALL |
55 | 63 | "break": { "OP": 0b000000, "FUNCT": 0b001101 }, # SPECIAL code BREAK | BREAK |
56 | | - "teq": { "OP": 0b000000, "FUNCT": 0b110100 }, |
57 | 64 |
|
58 | | - # 3 |
59 | | - "bgez": { "OP": 0b000001, "RT": 0b00001, "FUNCT": "unlimited" }, # REGIMM rs BGEZ offset | BGEZ rs, offset |
60 | | - "jr": { "OP": 0b000000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b001000 }, |
| 65 | + # 1 |
| 66 | + "teq": { "OP": 0b000000, "FUNCT": 0b110100 }, # SPECIAL rs rt code TEQ | TEQ rs, rt |
| 67 | + |
| 68 | + # 1 |
61 | 69 | "jalr": { "OP": 0b000000, "RT": 0b00000, "SA": 0b00000, "FUNCT": 0b001001 }, # SPECIAL rs 0 rd 0 JALR | JALR rs (rd = 31 implied) | JALR rd, rs |
62 | 70 |
|
63 | | - # 7 |
64 | | - "mfc0": { "OP": 0b010000, "RS": 0b00000, "SA": 0b00000, "FUNCT": 0b000000 }, |
65 | | - "mtc0": { "OP": 0b010000, "RS": 0b00100, "SA": 0b00000, "FUNCT": 0b000000 }, |
66 | | - "mfhi": { "OP": 0b000000, "RS": 0b00000, "RT": 0b00000, "SA": 0b00000, "FUNCT": 0b010000 }, |
67 | | - "mflo": { "OP": 0b000000, "RS": 0b00000, "RT": 0b00000, "SA": 0b00000, "FUNCT": 0b010010 }, |
68 | | - "mthi": { "OP": 0b000000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b010001 }, |
69 | | - "mtlo": { "OP": 0b000000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b010011 }, |
| 71 | + # 2 |
| 72 | + "mfhi": { "OP": 0b000000, "RS": 0b00000, "RT": 0b00000, "SA": 0b00000, "FUNCT": 0b010000 }, # SPECIAL 10{0} rd 0 MFHI | MFHI rd |
| 73 | + "mflo": { "OP": 0b000000, "RS": 0b00000, "RT": 0b00000, "SA": 0b00000, "FUNCT": 0b010010 }, # SPECIAL 10{0} rd 0 MFLO | MFLO rd |
| 74 | + |
| 75 | + # 3 |
| 76 | + "jr": { "OP": 0b000000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b001000 }, # SPECIAL rs 15{0} JR | JR rs |
| 77 | + "mthi": { "OP": 0b000000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b010001 }, # SPECIAL rs 15{0} MTHI | MTHI rs |
| 78 | + "mtlo": { "OP": 0b000000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b010011 }, # SPECIAL rs 15{0} MTLO | MTLO rs |
| 79 | + |
| 80 | + # 2 |
| 81 | + "mfc0": { "OP": 0b010000, "RS": 0b00000, "SA": 0b00000, "FUNCT": 0b000000 }, # COP0 MF rt fs 11{0} | MFC0 rt, fs |
| 82 | + "mtc0": { "OP": 0b010000, "RS": 0b00100, "SA": 0b00000, "FUNCT": 0b000000 }, # COP0 MT rt fs 11{0} | MTC0 rt, fs |
| 83 | + |
| 84 | + # 1 |
| 85 | + "bgez": { "OP": 0b000001, "RT": 0b00001, "FUNCT": "unlimited" }, # REGIMM rs rt(BGEZ) offset | BGEZ rs, offset |
70 | 86 |
|
71 | 87 | # 1 |
72 | 88 | "eret": { "OP": 0b100000, "RS": 0b10000, "RT": 0b00000, "RD": 0b00000, "SA": 0b00000, "FUNCT": 0b011000 }, |
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