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chore: fix formatting
1 parent dee8392 commit 1fc1bf5

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4 files changed

+26
-23
lines changed

4 files changed

+26
-23
lines changed

core/src/fr/hammons/slinc/Ptr.scala

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@ import scala.reflect.ClassTag
44
import fr.hammons.slinc.modules.DescriptorModule
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import fr.hammons.slinc.modules.ReadWriteModule
66

7-
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class Ptr[A](private[slinc] val mem: Mem, private[slinc] val offset: Bytes):
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inline def `unary_!`(using rwm: ReadWriteModule): A =
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import scala.compiletime.summonFrom

core/test/src/fr/hammons/slinc/TransferSpec.scala

Lines changed: 18 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -277,22 +277,25 @@ trait TransferSpec[ThreadException <: Throwable](val slinc: Slinc)(using
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assertEquals(res, 5)
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}
279279

280-
val randomA = for
280+
val randomA = for
281281
a <- Arbitrary.arbitrary[CInt]
282282
b <- Arbitrary.arbitrary[CInt]
283-
yield A(a,b)
284-
val randomUnion = Gen.oneOf[CInt | CFloat | A](Arbitrary.arbitrary[CInt], Arbitrary.arbitrary[CFloat], randomA)
283+
yield A(a, b)
284+
val randomUnion = Gen.oneOf[CInt | CFloat | A](
285+
Arbitrary.arbitrary[CInt],
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Arbitrary.arbitrary[CFloat],
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randomA
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)
285289

286290
property("Can send and receive data from a Union"):
287-
val union = CUnion[(CInt, CFloat, A)]
288-
forAll(randomUnion):
289-
case a: CInt =>
290-
union.set(a)
291-
assertEquals(a, union.get[CInt])
292-
case a: CFloat =>
293-
union.set(a)
294-
assertEquals(a, union.get[CFloat])
295-
case a: A =>
296-
union.set(a)
297-
assertEquals(a, union.get[A])
298-
291+
val union = CUnion[(CInt, CFloat, A)]
292+
forAll(randomUnion):
293+
case a: CInt =>
294+
union.set(a)
295+
assertEquals(a, union.get[CInt])
296+
case a: CFloat =>
297+
union.set(a)
298+
assertEquals(a, union.get[CFloat])
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case a: A =>
300+
union.set(a)
301+
assertEquals(a, union.get[A])

j17/src/fr/hammons/slinc/Scope17.scala

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,11 +54,11 @@ class Scope17(linker: CLinker) extends ScopeI.PlatformSpecific:
5454
res
5555

5656
def createInferredScope: InferredScope = new InferredScope:
57-
def apply[A](fn: Allocator ?=> A): A =
58-
val scope = ResourceScope.newImplicitScope().nn
57+
def apply[A](fn: Allocator ?=> A): A =
58+
val scope = ResourceScope.newImplicitScope().nn
5959
given Allocator = Allocator17(
60-
SegmentAllocator.arenaAllocator(scope).nn,
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SegmentAllocator.arenaAllocator(scope).nn,
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scope,
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linker
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)
64-
fn
64+
fn

j19/src/fr/hammons/slinc/Scope19.scala

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,8 @@ class Scope19(linker: Linker) extends ScopeI.PlatformSpecific:
5353
res
5454

5555
override def createInferredScope: InferredScope = new InferredScope:
56-
def apply[A](fn: Allocator ?=> A): A =
57-
val rs = MemorySession.openImplicit().nn
58-
given Allocator = Allocator19(SegmentAllocator.newNativeArena(rs).nn, rs, linker)
56+
def apply[A](fn: Allocator ?=> A): A =
57+
val rs = MemorySession.openImplicit().nn
58+
given Allocator =
59+
Allocator19(SegmentAllocator.newNativeArena(rs).nn, rs, linker)
5960
fn

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