Skip to content

Commit 715c303

Browse files
topperctopperc
authored
[RISCV][GISel] Support G_SEXT_INREG for Zbb. (llvm#102682)
1 parent a0be705 commit 715c303

File tree

9 files changed

+87
-137
lines changed

9 files changed

+87
-137
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1096,19 +1096,21 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI,
10961096

10971097
bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
10981098
MachineIRBuilder &MIB) const {
1099-
if (!STI.isRV64())
1100-
return false;
1101-
1102-
const MachineOperand &Size = MI.getOperand(2);
1103-
// Only Size == 32 (i.e. shift by 32 bits) is acceptable at this point.
1104-
if (!Size.isImm() || Size.getImm() != 32)
1105-
return false;
1106-
1107-
const MachineOperand &Src = MI.getOperand(1);
1108-
const MachineOperand &Dst = MI.getOperand(0);
1109-
// addiw rd, rs, 0 (i.e. sext.w rd, rs)
1110-
MachineInstr *NewMI =
1111-
MIB.buildInstr(RISCV::ADDIW, {Dst.getReg()}, {Src.getReg()}).addImm(0U);
1099+
Register DstReg = MI.getOperand(0).getReg();
1100+
Register SrcReg = MI.getOperand(1).getReg();
1101+
unsigned SrcSize = MI.getOperand(2).getImm();
1102+
1103+
MachineInstr *NewMI;
1104+
if (SrcSize == 32) {
1105+
assert(Subtarget->is64Bit() && "Unexpected extend");
1106+
// addiw rd, rs, 0 (i.e. sext.w rd, rs)
1107+
NewMI = MIB.buildInstr(RISCV::ADDIW, {DstReg}, {SrcReg}).addImm(0U);
1108+
} else {
1109+
assert(Subtarget->hasStdExtZbb() && "Unexpected extension");
1110+
assert((SrcSize == 8 || SrcSize == 16) && "Unexpected size");
1111+
unsigned Opc = SrcSize == 16 ? RISCV::SEXT_H : RISCV::SEXT_B;
1112+
NewMI = MIB.buildInstr(Opc, {DstReg}, {SrcReg});
1113+
}
11121114

11131115
if (!constrainSelectedInstRegOperands(*NewMI, TII, TRI, RBI))
11141116
return false;

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -171,11 +171,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
171171
if (ST.is64Bit()) {
172172
ExtActions.legalFor({{sXLen, s32}});
173173
getActionDefinitionsBuilder(G_SEXT_INREG)
174-
.customFor({sXLen})
174+
.customFor({s32, sXLen})
175175
.maxScalar(0, sXLen)
176176
.lower();
177177
} else {
178-
getActionDefinitionsBuilder(G_SEXT_INREG).maxScalar(0, sXLen).lower();
178+
getActionDefinitionsBuilder(G_SEXT_INREG)
179+
.customFor({s32})
180+
.maxScalar(0, sXLen)
181+
.lower();
179182
}
180183
ExtActions.customIf(typeIsLegalBoolVec(1, BoolVecTys, ST))
181184
.maxScalar(0, sXLen);
@@ -869,6 +872,7 @@ bool RISCVLegalizerInfo::legalizeCustom(
869872
LegalizerHelper &Helper, MachineInstr &MI,
870873
LostDebugLocObserver &LocObserver) const {
871874
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
875+
MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
872876
GISelChangeObserver &Observer = Helper.Observer;
873877
MachineFunction &MF = *MI.getParent()->getParent();
874878
switch (MI.getOpcode()) {
@@ -893,9 +897,13 @@ bool RISCVLegalizerInfo::legalizeCustom(
893897
case TargetOpcode::G_LSHR:
894898
return legalizeShlAshrLshr(MI, MIRBuilder, Observer);
895899
case TargetOpcode::G_SEXT_INREG: {
896-
// Source size of 32 is sext.w.
900+
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
897901
int64_t SizeInBits = MI.getOperand(2).getImm();
898-
if (SizeInBits == 32)
902+
// Source size of 32 is sext.w.
903+
if (DstTy.getSizeInBits() == 64 && SizeInBits == 32)
904+
return true;
905+
906+
if (STI.hasStdExtZbb() && (SizeInBits == 8 || SizeInBits == 16))
899907
return true;
900908

901909
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==

‎llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,7 @@ define i8 @abs8(i8 %x) {
2525
;
2626
; RV32ZBB-LABEL: abs8:
2727
; RV32ZBB: # %bb.0:
28-
; RV32ZBB-NEXT: slli a0, a0, 24
29-
; RV32ZBB-NEXT: srai a0, a0, 24
28+
; RV32ZBB-NEXT: sext.b a0, a0
3029
; RV32ZBB-NEXT: neg a1, a0
3130
; RV32ZBB-NEXT: max a0, a0, a1
3231
; RV32ZBB-NEXT: ret
@@ -42,8 +41,7 @@ define i8 @abs8(i8 %x) {
4241
;
4342
; RV64ZBB-LABEL: abs8:
4443
; RV64ZBB: # %bb.0:
45-
; RV64ZBB-NEXT: slli a0, a0, 56
46-
; RV64ZBB-NEXT: srai a0, a0, 56
44+
; RV64ZBB-NEXT: sext.b a0, a0
4745
; RV64ZBB-NEXT: neg a1, a0
4846
; RV64ZBB-NEXT: max a0, a0, a1
4947
; RV64ZBB-NEXT: ret
@@ -63,8 +61,7 @@ define i16 @abs16(i16 %x) {
6361
;
6462
; RV32ZBB-LABEL: abs16:
6563
; RV32ZBB: # %bb.0:
66-
; RV32ZBB-NEXT: slli a0, a0, 16
67-
; RV32ZBB-NEXT: srai a0, a0, 16
64+
; RV32ZBB-NEXT: sext.h a0, a0
6865
; RV32ZBB-NEXT: neg a1, a0
6966
; RV32ZBB-NEXT: max a0, a0, a1
7067
; RV32ZBB-NEXT: ret
@@ -80,8 +77,7 @@ define i16 @abs16(i16 %x) {
8077
;
8178
; RV64ZBB-LABEL: abs16:
8279
; RV64ZBB: # %bb.0:
83-
; RV64ZBB-NEXT: slli a0, a0, 48
84-
; RV64ZBB-NEXT: srai a0, a0, 48
80+
; RV64ZBB-NEXT: sext.h a0, a0
8581
; RV64ZBB-NEXT: neg a1, a0
8682
; RV64ZBB-NEXT: max a0, a0, a1
8783
; RV64ZBB-NEXT: ret

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -26,14 +26,12 @@ body: |
2626
; RV32ZBB-LABEL: name: abs_i8
2727
; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
2828
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
29-
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
30-
; RV32ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)
31-
; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
32-
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
33-
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[ASHR]]
34-
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[SUB]]
35-
; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
36-
; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C2]]
29+
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASSERT_ZEXT]], 8
30+
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
31+
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SEXT_INREG]]
32+
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SUB]]
33+
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
34+
; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C1]]
3735
; RV32ZBB-NEXT: $x10 = COPY [[AND]](s32)
3836
; RV32ZBB-NEXT: PseudoRET implicit $x10
3937
%1:_(s32) = COPY $x10
@@ -67,10 +65,8 @@ body: |
6765
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
6866
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ASSERT_SEXT]]
6967
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[SUB]]
70-
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
71-
; RV32ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C1]](s32)
72-
; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
73-
; RV32ZBB-NEXT: $x10 = COPY [[ASHR]](s32)
68+
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 16
69+
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s32)
7470
; RV32ZBB-NEXT: PseudoRET implicit $x10
7571
%1:_(s32) = COPY $x10
7672
%2:_(s32) = G_ASSERT_SEXT %1, 16

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -30,14 +30,12 @@ body: |
3030
; RV64ZBB-LABEL: name: abs_i8
3131
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3232
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
33-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
34-
; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C]](s64)
35-
; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
36-
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
37-
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C1]], [[ASHR]]
38-
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASHR]], [[SUB]]
39-
; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
40-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SMAX]], [[C2]]
33+
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT]], 8
34+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
35+
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[SEXT_INREG]]
36+
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SUB]]
37+
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
38+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SMAX]], [[C1]]
4139
; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64)
4240
; RV64ZBB-NEXT: PseudoRET implicit $x10
4341
%1:_(s64) = COPY $x10
@@ -74,10 +72,8 @@ body: |
7472
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
7573
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[ASSERT_SEXT]]
7674
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[SUB]]
77-
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
78-
; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SMAX]], [[C1]](s64)
79-
; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
80-
; RV64ZBB-NEXT: $x10 = COPY [[ASHR]](s64)
75+
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 16
76+
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
8177
; RV64ZBB-NEXT: PseudoRET implicit $x10
8278
%1:_(s64) = COPY $x10
8379
%2:_(s64) = G_ASSERT_SEXT %1, 16

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir‎

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -27,17 +27,11 @@ body: |
2727
; RV32ZBB-LABEL: name: smax_i8
2828
; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
2929
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
30-
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
31-
; RV32ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
32-
; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
33-
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
34-
; RV32ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
35-
; RV32ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
36-
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
37-
; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
38-
; RV32ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C2]](s32)
39-
; RV32ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
40-
; RV32ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
30+
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
31+
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
32+
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
33+
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 8
34+
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
4135
; RV32ZBB-NEXT: PseudoRET implicit $x10
4236
%0:_(s32) = COPY $x10
4337
%1:_(s32) = COPY $x11
@@ -73,17 +67,11 @@ body: |
7367
; RV32ZBB-LABEL: name: smax_i16
7468
; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
7569
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
76-
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
77-
; RV32ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
78-
; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
79-
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
80-
; RV32ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
81-
; RV32ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
82-
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
83-
; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
84-
; RV32ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMAX]], [[C2]](s32)
85-
; RV32ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
86-
; RV32ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
70+
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
71+
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
72+
; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
73+
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 16
74+
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
8775
; RV32ZBB-NEXT: PseudoRET implicit $x10
8876
%0:_(s32) = COPY $x10
8977
%1:_(s32) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv64.mir‎

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -30,17 +30,11 @@ body: |
3030
; RV64ZBB-LABEL: name: smax_i8
3131
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3232
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
33-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
34-
; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
35-
; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
36-
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
37-
; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
38-
; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
39-
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASHR]], [[ASHR1]]
40-
; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
41-
; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMAX]], [[C2]](s64)
42-
; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
43-
; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
33+
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
34+
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
35+
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
36+
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 8
37+
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
4438
; RV64ZBB-NEXT: PseudoRET implicit $x10
4539
%0:_(s64) = COPY $x10
4640
%1:_(s64) = COPY $x11
@@ -79,17 +73,11 @@ body: |
7973
; RV64ZBB-LABEL: name: smax_i16
8074
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
8175
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
82-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
83-
; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
84-
; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
85-
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
86-
; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
87-
; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
88-
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASHR]], [[ASHR1]]
89-
; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
90-
; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMAX]], [[C2]](s64)
91-
; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
92-
; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
76+
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
77+
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16
78+
; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
79+
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 16
80+
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
9381
; RV64ZBB-NEXT: PseudoRET implicit $x10
9482
%0:_(s64) = COPY $x10
9583
%1:_(s64) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir‎

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -27,17 +27,11 @@ body: |
2727
; RV32ZBB-LABEL: name: smin_i8
2828
; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
2929
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
30-
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
31-
; RV32ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
32-
; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
33-
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
34-
; RV32ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
35-
; RV32ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
36-
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
37-
; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
38-
; RV32ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMIN]], [[C2]](s32)
39-
; RV32ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
40-
; RV32ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
30+
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
31+
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
32+
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
33+
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMIN]], 8
34+
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
4135
; RV32ZBB-NEXT: PseudoRET implicit $x10
4236
%0:_(s32) = COPY $x10
4337
%1:_(s32) = COPY $x11
@@ -73,17 +67,11 @@ body: |
7367
; RV32ZBB-LABEL: name: smin_i16
7468
; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
7569
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
76-
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
77-
; RV32ZBB-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
78-
; RV32ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
79-
; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
80-
; RV32ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
81-
; RV32ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
82-
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
83-
; RV32ZBB-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
84-
; RV32ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SMIN]], [[C2]](s32)
85-
; RV32ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C2]](s32)
86-
; RV32ZBB-NEXT: $x10 = COPY [[ASHR2]](s32)
70+
; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
71+
; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
72+
; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
73+
; RV32ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMIN]], 16
74+
; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s32)
8775
; RV32ZBB-NEXT: PseudoRET implicit $x10
8876
%0:_(s32) = COPY $x10
8977
%1:_(s32) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv64.mir‎

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -30,17 +30,11 @@ body: |
3030
; RV64ZBB-LABEL: name: smin_i8
3131
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3232
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
33-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
34-
; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
35-
; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
36-
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
37-
; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
38-
; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
39-
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
40-
; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
41-
; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
42-
; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
43-
; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
33+
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 8
34+
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
35+
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
36+
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 8
37+
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
4438
; RV64ZBB-NEXT: PseudoRET implicit $x10
4539
%0:_(s64) = COPY $x10
4640
%1:_(s64) = COPY $x11
@@ -79,17 +73,11 @@ body: |
7973
; RV64ZBB-LABEL: name: smin_i16
8074
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
8175
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
82-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
83-
; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
84-
; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
85-
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
86-
; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
87-
; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
88-
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
89-
; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
90-
; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
91-
; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
92-
; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
76+
; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 16
77+
; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 16
78+
; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
79+
; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 16
80+
; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
9381
; RV64ZBB-NEXT: PseudoRET implicit $x10
9482
%0:_(s64) = COPY $x10
9583
%1:_(s64) = COPY $x11

0 commit comments

Comments
 (0)