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sandeepmistrysandeepmistry
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implement Wire.end() for SAM core
also moved common reset and disable code in libsam TWI_ConfigureMaster and TWI_ConfigureSlave functions to new TWI_Disable function, which is used in TwoWire::end()
1 parent 64cee7b commit 889da8f

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6 files changed

+68
-51
lines changed

6 files changed

+68
-51
lines changed

‎hardware/arduino/sam/libraries/Wire/Wire.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -126,6 +126,10 @@ void TwoWire::begin(int address) {
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begin((uint8_t) address);
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}
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129+
void TwoWire::end(void) {
130+
TWI_Disable(twi);
131+
}
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129133
void TwoWire::setClock(uint32_t frequency) {
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twiClock = frequency;
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TWI_SetClock(twi, twiClock, VARIANT_MCK);

‎hardware/arduino/sam/libraries/Wire/Wire.h‎

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Original file line numberDiff line numberDiff line change
@@ -29,12 +29,16 @@
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#define BUFFER_LENGTH 32
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32+
// WIRE_HAS_END means Wire has end()
33+
#define WIRE_HAS_END 1
34+
3235
class TwoWire : public Stream {
3336
public:
3437
TwoWire(Twi *twi, void(*begin_cb)(void));
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void begin();
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void begin(uint8_t);
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void begin(int);
41+
void end();
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void setClock(uint32_t);
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void beginTransmission(uint8_t);
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void beginTransmission(int);

‎hardware/arduino/sam/system/libsam/include/twi.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,8 @@ extern void TWI_SetClock( Twi *pTwi, uint32_t dwTwCk, uint32_t dwMCk );
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extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress);
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74+
extern void TWI_Disable(Twi *pTwi);
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extern void TWI_Stop(Twi *pTwi);
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extern void TWI_StartRead(

‎hardware/arduino/sam/system/libsam/source/twi.c‎

Lines changed: 23 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -100,13 +100,8 @@ void TWI_ConfigureMaster( Twi* pTwi, uint32_t dwTwCk, uint32_t dwMCk )
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/* SVEN: TWI Slave Mode Enabled */
102102
pTwi->TWI_CR = TWI_CR_SVEN ;
103-
/* Reset the TWI */
104-
pTwi->TWI_CR = TWI_CR_SWRST ;
105-
pTwi->TWI_RHR ;
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107-
/* TWI Slave Mode Disabled, TWI Master Mode Disabled. */
108-
pTwi->TWI_CR = TWI_CR_SVDIS ;
109-
pTwi->TWI_CR = TWI_CR_MSDIS ;
104+
TWI_Disable(pTwi);
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/* Set master mode */
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pTwi->TWI_CR = TWI_CR_MSEN ;
@@ -156,15 +151,7 @@ void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress)
156151
{
157152
uint32_t i;
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159-
/* TWI software reset */
160-
pTwi->TWI_CR = TWI_CR_SWRST;
161-
pTwi->TWI_RHR;
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/* Wait at least 10 ms */
164-
for (i=0; i < 1000000; i++);
165-
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/* TWI Slave Mode Disabled, TWI Master Mode Disabled*/
167-
pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS;
154+
TWI_Disable(pTwi);
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169156
/* Configure slave address. */
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pTwi->TWI_SMR = 0;
@@ -178,6 +165,27 @@ void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress)
178165
assert( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS ) ;
179166
}
180167

168+
/**
169+
* \brief Disables the TWI.
170+
* \param pTwi Pointer to an Twi instance.
171+
*/
172+
void TWI_Disable(Twi *pTwi)
173+
{
174+
assert( pTwi ) ;
175+
176+
uint32_t i;
177+
178+
/* TWI software reset */
179+
pTwi->TWI_CR = TWI_CR_SWRST;
180+
pTwi->TWI_RHR;
181+
182+
/* Wait at least 10 ms */
183+
for (i=0; i < 1000000; i++);
184+
185+
/* TWI Slave Mode Disabled, TWI Master Mode Disabled*/
186+
pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS;
187+
}
188+
181189
/**
182190
* \brief Sends a STOP condition on the TWI.
183191
* \param pTwi Pointer to an Twi instance.

‎hardware/arduino/sam/variants/arduino_due_x/libsam_sam3x8e_gcc_rel.a‎

546 Bytes
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‎hardware/arduino/sam/variants/arduino_due_x/libsam_sam3x8e_gcc_rel.a.txt‎

Lines changed: 35 additions & 36 deletions
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@@ -72,7 +72,6 @@ pmc.o:
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00000000 T pmc_switch_udpck_to_upllck
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pwmc.o:
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00000000 r C.9.8054
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00000000 t FindClockConfiguration
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00000000 T PWMC_ConfigureChannel
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00000000 T PWMC_ConfigureChannelExt
@@ -100,14 +99,14 @@ pwmc.o:
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00000000 T PWMC_SetSyncChannelUpdateUnlock
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00000000 T PWMC_WriteBuffer
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U __assert_func
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00000000 r __func__.6635
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00000000 r __func__.6646
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00000000 r __func__.6661
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00000000 r __func__.6672
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00000000 r __func__.6683
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00000000 r __func__.6690
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00000000 r __func__.6774
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00000000 r __func__.6780
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00000000 r __func__.6793
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00000000 r __func__.6804
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00000000 r __func__.6819
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00000000 r __func__.6830
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00000000 r __func__.6841
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00000000 r __func__.6848
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00000000 r __func__.6932
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00000000 r __func__.6938
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rtc.o:
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00000000 T RTC_ClearSCCR
@@ -123,9 +122,9 @@ rtc.o:
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00000000 T RTC_SetTime
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00000000 T RTC_SetTimeAlarm
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U __assert_func
126-
00000000 r __func__.6632
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00000000 r __func__.6641
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00000000 r __func__.6646
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00000000 r __func__.6790
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00000000 r __func__.6799
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00000000 r __func__.6804
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rtt.o:
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00000000 T RTT_EnableIT
@@ -134,8 +133,8 @@ rtt.o:
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00000000 T RTT_SetAlarm
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00000000 T RTT_SetPrescaler
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U __assert_func
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00000000 r __func__.6639
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00000000 r __func__.6647
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00000000 r __func__.6797
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00000000 r __func__.6805
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spi.o:
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00000000 T SPI_Configure
@@ -161,9 +160,9 @@ tc.o:
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00000000 T TC_Start
162161
00000000 T TC_Stop
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U __assert_func
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00000000 r __func__.6634
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00000000 r __func__.6640
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00000000 r __func__.6646
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00000000 r __func__.6792
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00000000 r __func__.6798
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00000000 r __func__.6804
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timetick.o:
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00000000 T GetTickCount
@@ -178,6 +177,7 @@ twi.o:
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00000000 T TWI_ByteSent
179178
00000000 T TWI_ConfigureMaster
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00000000 T TWI_ConfigureSlave
180+
00000000 T TWI_Disable
181181
00000000 T TWI_DisableIt
182182
00000000 T TWI_EnableIt
183183
00000000 T TWI_GetMaskedStatus
@@ -191,19 +191,20 @@ twi.o:
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00000000 T TWI_TransferComplete
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00000000 T TWI_WriteByte
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U __assert_func
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00000000 r __func__.7004
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00000000 r __func__.7010
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00000000 r __func__.7028
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00000000 r __func__.7032
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00000000 r __func__.7039
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00000000 r __func__.7043
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00000000 r __func__.7048
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00000000 r __func__.7056
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00000000 r __func__.7070
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00000000 r __func__.7075
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00000000 r __func__.7079
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00000000 r __func__.7084
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00000000 r __func__.7088
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00000000 r __func__.7151
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00000000 r __func__.7157
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00000000 r __func__.7172
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00000000 r __func__.7176
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00000000 r __func__.7184
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00000000 r __func__.7191
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00000000 r __func__.7195
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00000000 r __func__.7200
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00000000 r __func__.7208
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00000000 r __func__.7222
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00000000 r __func__.7227
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00000000 r __func__.7231
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00000000 r __func__.7236
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00000000 r __func__.7240
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usart.o:
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00000000 T USART_Configure
@@ -222,7 +223,7 @@ usart.o:
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00000000 T USART_Write
223224
00000000 T USART_WriteBuffer
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U __assert_func
225-
00000000 r __func__.6928
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00000000 r __func__.7068
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227228
wdt.o:
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00000000 T WDT_Disable
@@ -300,7 +301,6 @@ startup_sam3xa.o:
300301
U main
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adc.o:
303-
00000000 r C.0.8146
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00000000 T adc_configure_power_save
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00000000 T adc_configure_sequence
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00000000 T adc_configure_timing
@@ -485,12 +485,12 @@ efc.o:
485485
00000000 T efc_get_wait_state
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00000000 T efc_init
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00000000 T efc_perform_command
488-
00000070 T efc_perform_fcr
488+
0000006c T efc_perform_fcr
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00000000 T efc_perform_read_sequence
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00000000 T efc_set_flash_access_mode
491491
00000000 T efc_set_wait_state
492-
0000006c T efc_write_fmr
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00000000 b iap_perform_command.6909
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00000068 T efc_write_fmr
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00000000 b iap_perform_command.7049
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gpbr.o:
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00000000 T gpbr_read
@@ -568,7 +568,6 @@ emac.o:
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00000000 T emac_phy_write
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00000000 t emac_reset_rx_mem
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00000000 t emac_reset_tx_mem
571-
00000000 t emac_wait_phy.clone.1
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00000000 b gs_rx_desc
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00000000 b gs_tx_callback
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00000000 b gs_tx_desc

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