Update syntax of literal zero

rw-vanc · IsaacWoods · commit 8e71a960f79a · 2023-02-12T19:09:56.000Z
diff --git a/aml/src/value.rs b/aml/src/value.rs
@@ -286,7 +286,7 @@ impl AmlValue {
                 let bytes = bytes.lock();
                 let bytes = if bytes.len() > 8 { &bytes[0..8] } else { &bytes[..] };
 
-                Ok(bytes.iter().rev().fold(0: u64, |mut i, &popped| {
+                Ok(bytes.iter().rev().fold(0u64, |mut i, &popped| {
                     i <<= 8;
                     i += popped as u64;
                     i

Original file line number	Diff line number	Diff line change
`@@ -286,7 +286,7 @@ impl AmlValue {`
`286`	`286`	`let bytes = bytes.lock();`
`287`	`287`	`let bytes = if bytes.len() > 8 { &bytes[0..8] } else { &bytes[..] };`
`288`	`288`
`289`		`- Ok(bytes.iter().rev().fold(0: u64, \|mut i, &popped\| {`
	`289`	`+ Ok(bytes.iter().rev().fold(0u64, \|mut i, &popped\| {`
`290`	`290`	`i <<= 8;`
`291`	`291`	`i += popped as u64;`
`292`	`292`	`i`