Skip to content

Commit f8dfd22

Browse files
sayantnsayantn
committed
Fix CI errors due to alignment issues in msvc
1 parent e907456 commit f8dfd22

File tree

4 files changed

+35
-35
lines changed

4 files changed

+35
-35
lines changed

‎crates/core_arch/src/x86/avx.rs‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1425,7 +1425,7 @@ pub fn _mm256_insert_epi32<const INDEX: i32>(a: __m256i, i: i32) -> __m256i {
14251425
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_pd)
14261426
#[inline]
14271427
#[target_feature(enable = "avx")]
1428-
#[cfg_attr(test, assert_instr(vmovap))]
1428+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovap))]
14291429
#[stable(feature = "simd_x86", since = "1.27.0")]
14301430
#[allow(clippy::cast_ptr_alignment)]
14311431
pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
@@ -1440,7 +1440,7 @@ pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
14401440
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_pd)
14411441
#[inline]
14421442
#[target_feature(enable = "avx")]
1443-
#[cfg_attr(test, assert_instr(vmovap))]
1443+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovap))]
14441444
#[stable(feature = "simd_x86", since = "1.27.0")]
14451445
#[allow(clippy::cast_ptr_alignment)]
14461446
pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
@@ -1455,7 +1455,7 @@ pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
14551455
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_ps)
14561456
#[inline]
14571457
#[target_feature(enable = "avx")]
1458-
#[cfg_attr(test, assert_instr(vmovaps))]
1458+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))]
14591459
#[stable(feature = "simd_x86", since = "1.27.0")]
14601460
#[allow(clippy::cast_ptr_alignment)]
14611461
pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
@@ -1470,7 +1470,7 @@ pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
14701470
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_ps)
14711471
#[inline]
14721472
#[target_feature(enable = "avx")]
1473-
#[cfg_attr(test, assert_instr(vmovaps))]
1473+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))]
14741474
#[stable(feature = "simd_x86", since = "1.27.0")]
14751475
#[allow(clippy::cast_ptr_alignment)]
14761476
pub unsafe fn _mm256_store_ps(mem_addr: *mut f32, a: __m256) {
@@ -1548,7 +1548,7 @@ pub unsafe fn _mm256_storeu_ps(mem_addr: *mut f32, a: __m256) {
15481548
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_si256)
15491549
#[inline]
15501550
#[target_feature(enable = "avx")]
1551-
#[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovdqa expected
1551+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] // FIXME vmovdqa expected
15521552
#[stable(feature = "simd_x86", since = "1.27.0")]
15531553
pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
15541554
*mem_addr
@@ -1561,7 +1561,7 @@ pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
15611561
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_si256)
15621562
#[inline]
15631563
#[target_feature(enable = "avx")]
1564-
#[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovdqa expected
1564+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] // FIXME vmovdqa expected
15651565
#[stable(feature = "simd_x86", since = "1.27.0")]
15661566
pub unsafe fn _mm256_store_si256(mem_addr: *mut __m256i, a: __m256i) {
15671567
*mem_addr = a;

‎crates/core_arch/src/x86/avx512f.rs‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -34468,7 +34468,7 @@ pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) {
3446834468
#[inline]
3446934469
#[target_feature(enable = "avx512f")]
3447034470
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34471-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34471+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3447234472
pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
3447334473
ptr::read(mem_addr)
3447434474
}
@@ -34479,7 +34479,7 @@ pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
3447934479
#[inline]
3448034480
#[target_feature(enable = "avx512f")]
3448134481
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34482-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34482+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3448334483
pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
3448434484
ptr::write(mem_addr, a);
3448534485
}
@@ -34490,7 +34490,7 @@ pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
3449034490
#[inline]
3449134491
#[target_feature(enable = "avx512f")]
3449234492
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34493-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34493+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3449434494
pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
3449534495
ptr::read(mem_addr as *const __m512i)
3449634496
}
@@ -34501,7 +34501,7 @@ pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
3450134501
#[inline]
3450234502
#[target_feature(enable = "avx512f,avx512vl")]
3450334503
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34504-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34504+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3450534505
pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
3450634506
ptr::read(mem_addr as *const __m256i)
3450734507
}
@@ -34512,7 +34512,7 @@ pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
3451234512
#[inline]
3451334513
#[target_feature(enable = "avx512f,avx512vl")]
3451434514
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34515-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34515+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3451634516
pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
3451734517
ptr::read(mem_addr as *const __m128i)
3451834518
}
@@ -34523,7 +34523,7 @@ pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
3452334523
#[inline]
3452434524
#[target_feature(enable = "avx512f")]
3452534525
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34526-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34526+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3452734527
pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
3452834528
ptr::write(mem_addr as *mut __m512i, a);
3452934529
}
@@ -34534,7 +34534,7 @@ pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
3453434534
#[inline]
3453534535
#[target_feature(enable = "avx512f,avx512vl")]
3453634536
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34537-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34537+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3453834538
pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
3453934539
ptr::write(mem_addr as *mut __m256i, a);
3454034540
}
@@ -34545,7 +34545,7 @@ pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
3454534545
#[inline]
3454634546
#[target_feature(enable = "avx512f,avx512vl")]
3454734547
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34548-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34548+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa32
3454934549
pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
3455034550
ptr::write(mem_addr as *mut __m128i, a);
3455134551
}
@@ -34556,7 +34556,7 @@ pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
3455634556
#[inline]
3455734557
#[target_feature(enable = "avx512f")]
3455834558
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34559-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34559+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa64
3456034560
pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
3456134561
ptr::read(mem_addr as *const __m512i)
3456234562
}
@@ -34567,7 +34567,7 @@ pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
3456734567
#[inline]
3456834568
#[target_feature(enable = "avx512f,avx512vl")]
3456934569
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34570-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34570+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa64
3457134571
pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
3457234572
ptr::read(mem_addr as *const __m256i)
3457334573
}
@@ -34578,7 +34578,7 @@ pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
3457834578
#[inline]
3457934579
#[target_feature(enable = "avx512f,avx512vl")]
3458034580
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34581-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34581+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa64
3458234582
pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
3458334583
ptr::read(mem_addr as *const __m128i)
3458434584
}
@@ -34589,7 +34589,7 @@ pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
3458934589
#[inline]
3459034590
#[target_feature(enable = "avx512f")]
3459134591
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34592-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34592+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa64
3459334593
pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
3459434594
ptr::write(mem_addr as *mut __m512i, a);
3459534595
}
@@ -34600,7 +34600,7 @@ pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
3460034600
#[inline]
3460134601
#[target_feature(enable = "avx512f,avx512vl")]
3460234602
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34603-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34603+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa64
3460434604
pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
3460534605
ptr::write(mem_addr as *mut __m256i, a);
3460634606
}
@@ -34611,7 +34611,7 @@ pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
3461134611
#[inline]
3461234612
#[target_feature(enable = "avx512f,avx512vl")]
3461334613
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34614-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34614+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovdqa64
3461534615
pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
3461634616
ptr::write(mem_addr as *mut __m128i, a);
3461734617
}
@@ -34622,7 +34622,7 @@ pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
3462234622
#[inline]
3462334623
#[target_feature(enable = "avx512f")]
3462434624
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34625-
#[cfg_attr(test, assert_instr(vmovaps))]
34625+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))]
3462634626
pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
3462734627
ptr::read(mem_addr as *const __m512)
3462834628
}
@@ -34633,7 +34633,7 @@ pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
3463334633
#[inline]
3463434634
#[target_feature(enable = "avx512f")]
3463534635
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34636-
#[cfg_attr(test, assert_instr(vmovaps))]
34636+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))]
3463734637
pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
3463834638
ptr::write(mem_addr as *mut __m512, a);
3463934639
}
@@ -34644,7 +34644,7 @@ pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
3464434644
#[inline]
3464534645
#[target_feature(enable = "avx512f")]
3464634646
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34647-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovapd
34647+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovapd
3464834648
pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
3464934649
ptr::read(mem_addr as *const __m512d)
3465034650
}
@@ -34655,7 +34655,7 @@ pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
3465534655
#[inline]
3465634656
#[target_feature(enable = "avx512f")]
3465734657
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34658-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovapd
34658+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(vmovaps))] //should be vmovapd
3465934659
pub unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) {
3466034660
ptr::write(mem_addr as *mut __m512d, a);
3466134661
}

‎crates/core_arch/src/x86/sse.rs‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1158,7 +1158,7 @@ pub unsafe fn _mm_load_ps1(p: *const f32) -> __m128 {
11581158
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_ps)
11591159
#[inline]
11601160
#[target_feature(enable = "sse")]
1161-
#[cfg_attr(test, assert_instr(movaps))]
1161+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
11621162
#[stable(feature = "simd_x86", since = "1.27.0")]
11631163
#[allow(clippy::cast_ptr_alignment)]
11641164
pub unsafe fn _mm_load_ps(p: *const f32) -> __m128 {
@@ -1213,7 +1213,7 @@ pub unsafe fn _mm_loadu_ps(p: *const f32) -> __m128 {
12131213
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadr_ps)
12141214
#[inline]
12151215
#[target_feature(enable = "sse")]
1216-
#[cfg_attr(test, assert_instr(movaps))]
1216+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
12171217
#[stable(feature = "simd_x86", since = "1.27.0")]
12181218
pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
12191219
let a = _mm_load_ps(p);
@@ -1253,7 +1253,7 @@ pub unsafe fn _mm_store_ss(p: *mut f32, a: __m128) {
12531253
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store1_ps)
12541254
#[inline]
12551255
#[target_feature(enable = "sse")]
1256-
#[cfg_attr(test, assert_instr(movaps))]
1256+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
12571257
#[stable(feature = "simd_x86", since = "1.27.0")]
12581258
#[allow(clippy::cast_ptr_alignment)]
12591259
pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
@@ -1266,7 +1266,7 @@ pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
12661266
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_ps1)
12671267
#[inline]
12681268
#[target_feature(enable = "sse")]
1269-
#[cfg_attr(test, assert_instr(movaps))]
1269+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
12701270
#[stable(feature = "simd_x86", since = "1.27.0")]
12711271
pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
12721272
_mm_store1_ps(p, a);
@@ -1285,7 +1285,7 @@ pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
12851285
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_ps)
12861286
#[inline]
12871287
#[target_feature(enable = "sse")]
1288-
#[cfg_attr(test, assert_instr(movaps))]
1288+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
12891289
#[stable(feature = "simd_x86", since = "1.27.0")]
12901290
#[allow(clippy::cast_ptr_alignment)]
12911291
pub unsafe fn _mm_store_ps(p: *mut f32, a: __m128) {
@@ -1329,7 +1329,7 @@ pub unsafe fn _mm_storeu_ps(p: *mut f32, a: __m128) {
13291329
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storer_ps)
13301330
#[inline]
13311331
#[target_feature(enable = "sse")]
1332-
#[cfg_attr(test, assert_instr(movaps))]
1332+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
13331333
#[stable(feature = "simd_x86", since = "1.27.0")]
13341334
#[allow(clippy::cast_ptr_alignment)]
13351335
pub unsafe fn _mm_storer_ps(p: *mut f32, a: __m128) {

‎crates/core_arch/src/x86/sse2.rs‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1243,7 +1243,7 @@ pub unsafe fn _mm_loadl_epi64(mem_addr: *const __m128i) -> __m128i {
12431243
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_si128)
12441244
#[inline]
12451245
#[target_feature(enable = "sse2")]
1246-
#[cfg_attr(test, assert_instr(movaps))]
1246+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
12471247
#[stable(feature = "simd_x86", since = "1.27.0")]
12481248
pub unsafe fn _mm_load_si128(mem_addr: *const __m128i) -> __m128i {
12491249
*mem_addr
@@ -1293,7 +1293,7 @@ pub unsafe fn _mm_maskmoveu_si128(a: __m128i, mask: __m128i, mem_addr: *mut i8)
12931293
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_si128)
12941294
#[inline]
12951295
#[target_feature(enable = "sse2")]
1296-
#[cfg_attr(test, assert_instr(movaps))]
1296+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
12971297
#[stable(feature = "simd_x86", since = "1.27.0")]
12981298
pub unsafe fn _mm_store_si128(mem_addr: *mut __m128i, a: __m128i) {
12991299
*mem_addr = a;
@@ -2535,7 +2535,7 @@ pub fn _mm_movemask_pd(a: __m128d) -> i32 {
25352535
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_pd)
25362536
#[inline]
25372537
#[target_feature(enable = "sse2")]
2538-
#[cfg_attr(test, assert_instr(movaps))]
2538+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
25392539
#[stable(feature = "simd_x86", since = "1.27.0")]
25402540
#[allow(clippy::cast_ptr_alignment)]
25412541
pub unsafe fn _mm_load_pd(mem_addr: *const f64) -> __m128d {
@@ -2628,7 +2628,7 @@ pub unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) {
26282628
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_pd)
26292629
#[inline]
26302630
#[target_feature(enable = "sse2")]
2631-
#[cfg_attr(test, assert_instr(movaps))]
2631+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
26322632
#[stable(feature = "simd_x86", since = "1.27.0")]
26332633
#[allow(clippy::cast_ptr_alignment)]
26342634
pub unsafe fn _mm_store_pd(mem_addr: *mut f64, a: __m128d) {
@@ -2783,7 +2783,7 @@ pub unsafe fn _mm_load_pd1(mem_addr: *const f64) -> __m128d {
27832783
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadr_pd)
27842784
#[inline]
27852785
#[target_feature(enable = "sse2")]
2786-
#[cfg_attr(test, assert_instr(movaps))]
2786+
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(movaps))]
27872787
#[stable(feature = "simd_x86", since = "1.27.0")]
27882788
pub unsafe fn _mm_loadr_pd(mem_addr: *const f64) -> __m128d {
27892789
let a = _mm_load_pd(mem_addr);

0 commit comments

Comments
 (0)