@@ -7602,6 +7602,26 @@ pub unsafe fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
76027602 transmute(simd_add(transmute(a), b))
76037603}
76047604
7605+ /// Insert vector element from another vector element
7606+ #[inline]
7607+ #[target_feature(enable = "neon")]
7608+ #[cfg_attr(test, assert_instr(nop, LANE = 0))]
7609+ #[rustc_legacy_const_generics(2)]
7610+ pub unsafe fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t {
7611+ static_assert!(LANE : i32 where LANE == 0);
7612+ simd_insert(b, LANE as u32, a)
7613+ }
7614+
7615+ /// Insert vector element from another vector element
7616+ #[inline]
7617+ #[target_feature(enable = "neon")]
7618+ #[cfg_attr(test, assert_instr(nop, LANE = 0))]
7619+ #[rustc_legacy_const_generics(2)]
7620+ pub unsafe fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
7621+ static_assert_imm1!(LANE);
7622+ simd_insert(b, LANE as u32, a)
7623+ }
7624+
76057625/// Signed Shift left
76067626#[inline]
76077627#[target_feature(enable = "neon")]
@@ -15111,6 +15131,24 @@ mod test {
1511115131 assert_eq!(r, e);
1511215132 }
1511315133
15134+ #[simd_test(enable = "neon")]
15135+ unsafe fn test_vset_lane_f64() {
15136+ let a: f64 = 1.;
15137+ let b: f64 = 0.;
15138+ let e: f64 = 1.;
15139+ let r: f64 = transmute(vset_lane_f64::<0>(transmute(a), transmute(b)));
15140+ assert_eq!(r, e);
15141+ }
15142+
15143+ #[simd_test(enable = "neon")]
15144+ unsafe fn test_vsetq_lane_f64() {
15145+ let a: f64 = 1.;
15146+ let b: f64x2 = f64x2::new(0., 2.);
15147+ let e: f64x2 = f64x2::new(1., 2.);
15148+ let r: f64x2 = transmute(vsetq_lane_f64::<0>(transmute(a), transmute(b)));
15149+ assert_eq!(r, e);
15150+ }
15151+
1511415152 #[simd_test(enable = "neon")]
1511515153 unsafe fn test_vshld_s64() {
1511615154 let a: i64 = 1;
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