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AmanieuAmanieu
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Stabilize AArch64 AES/SHA1/SHA2 intrinsics
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‎crates/core_arch/src/arm_shared/crypto.rs‎

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,13 @@ use stdarch_test::assert_instr;
5858
#[target_feature(enable = "aes")]
5959
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6060
#[cfg_attr(test, assert_instr(aese))]
61+
#[cfg_attr(
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not(target_arch = "arm"),
63+
stable(
64+
feature = "aarch64_neon_crypto_intrinsics",
65+
since = "CURRENT_RUSTC_VERSION"
66+
)
67+
)]
6168
pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
6269
vaeseq_u8_(data, key)
6370
}
@@ -69,6 +76,13 @@ pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
6976
#[target_feature(enable = "aes")]
7077
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
7178
#[cfg_attr(test, assert_instr(aesd))]
79+
#[cfg_attr(
80+
not(target_arch = "arm"),
81+
stable(
82+
feature = "aarch64_neon_crypto_intrinsics",
83+
since = "CURRENT_RUSTC_VERSION"
84+
)
85+
)]
7286
pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
7387
vaesdq_u8_(data, key)
7488
}
@@ -80,6 +94,13 @@ pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
8094
#[target_feature(enable = "aes")]
8195
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8296
#[cfg_attr(test, assert_instr(aesmc))]
97+
#[cfg_attr(
98+
not(target_arch = "arm"),
99+
stable(
100+
feature = "aarch64_neon_crypto_intrinsics",
101+
since = "CURRENT_RUSTC_VERSION"
102+
)
103+
)]
83104
pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
84105
vaesmcq_u8_(data)
85106
}
@@ -91,6 +112,13 @@ pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
91112
#[target_feature(enable = "aes")]
92113
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
93114
#[cfg_attr(test, assert_instr(aesimc))]
115+
#[cfg_attr(
116+
not(target_arch = "arm"),
117+
stable(
118+
feature = "aarch64_neon_crypto_intrinsics",
119+
since = "CURRENT_RUSTC_VERSION"
120+
)
121+
)]
94122
pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
95123
vaesimcq_u8_(data)
96124
}
@@ -102,6 +130,13 @@ pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
102130
#[target_feature(enable = "sha2")]
103131
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
104132
#[cfg_attr(test, assert_instr(sha1h))]
133+
#[cfg_attr(
134+
not(target_arch = "arm"),
135+
stable(
136+
feature = "aarch64_neon_crypto_intrinsics",
137+
since = "CURRENT_RUSTC_VERSION"
138+
)
139+
)]
105140
pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
106141
vsha1h_u32_(hash_e)
107142
}
@@ -113,6 +148,13 @@ pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
113148
#[target_feature(enable = "sha2")]
114149
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
115150
#[cfg_attr(test, assert_instr(sha1c))]
151+
#[cfg_attr(
152+
not(target_arch = "arm"),
153+
stable(
154+
feature = "aarch64_neon_crypto_intrinsics",
155+
since = "CURRENT_RUSTC_VERSION"
156+
)
157+
)]
116158
pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
117159
vsha1cq_u32_(hash_abcd, hash_e, wk)
118160
}
@@ -124,6 +166,13 @@ pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
124166
#[target_feature(enable = "sha2")]
125167
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
126168
#[cfg_attr(test, assert_instr(sha1m))]
169+
#[cfg_attr(
170+
not(target_arch = "arm"),
171+
stable(
172+
feature = "aarch64_neon_crypto_intrinsics",
173+
since = "CURRENT_RUSTC_VERSION"
174+
)
175+
)]
127176
pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
128177
vsha1mq_u32_(hash_abcd, hash_e, wk)
129178
}
@@ -135,6 +184,13 @@ pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
135184
#[target_feature(enable = "sha2")]
136185
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
137186
#[cfg_attr(test, assert_instr(sha1p))]
187+
#[cfg_attr(
188+
not(target_arch = "arm"),
189+
stable(
190+
feature = "aarch64_neon_crypto_intrinsics",
191+
since = "CURRENT_RUSTC_VERSION"
192+
)
193+
)]
138194
pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
139195
vsha1pq_u32_(hash_abcd, hash_e, wk)
140196
}
@@ -146,6 +202,13 @@ pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) ->
146202
#[target_feature(enable = "sha2")]
147203
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
148204
#[cfg_attr(test, assert_instr(sha1su0))]
205+
#[cfg_attr(
206+
not(target_arch = "arm"),
207+
stable(
208+
feature = "aarch64_neon_crypto_intrinsics",
209+
since = "CURRENT_RUSTC_VERSION"
210+
)
211+
)]
149212
pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
150213
vsha1su0q_u32_(w0_3, w4_7, w8_11)
151214
}
@@ -157,6 +220,13 @@ pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_
157220
#[target_feature(enable = "sha2")]
158221
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
159222
#[cfg_attr(test, assert_instr(sha1su1))]
223+
#[cfg_attr(
224+
not(target_arch = "arm"),
225+
stable(
226+
feature = "aarch64_neon_crypto_intrinsics",
227+
since = "CURRENT_RUSTC_VERSION"
228+
)
229+
)]
160230
pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
161231
vsha1su1q_u32_(tw0_3, w12_15)
162232
}
@@ -168,6 +238,13 @@ pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t
168238
#[target_feature(enable = "sha2")]
169239
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
170240
#[cfg_attr(test, assert_instr(sha256h))]
241+
#[cfg_attr(
242+
not(target_arch = "arm"),
243+
stable(
244+
feature = "aarch64_neon_crypto_intrinsics",
245+
since = "CURRENT_RUSTC_VERSION"
246+
)
247+
)]
171248
pub unsafe fn vsha256hq_u32(
172249
hash_abcd: uint32x4_t,
173250
hash_efgh: uint32x4_t,
@@ -183,6 +260,13 @@ pub unsafe fn vsha256hq_u32(
183260
#[target_feature(enable = "sha2")]
184261
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
185262
#[cfg_attr(test, assert_instr(sha256h2))]
263+
#[cfg_attr(
264+
not(target_arch = "arm"),
265+
stable(
266+
feature = "aarch64_neon_crypto_intrinsics",
267+
since = "CURRENT_RUSTC_VERSION"
268+
)
269+
)]
186270
pub unsafe fn vsha256h2q_u32(
187271
hash_efgh: uint32x4_t,
188272
hash_abcd: uint32x4_t,
@@ -198,6 +282,13 @@ pub unsafe fn vsha256h2q_u32(
198282
#[target_feature(enable = "sha2")]
199283
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
200284
#[cfg_attr(test, assert_instr(sha256su0))]
285+
#[cfg_attr(
286+
not(target_arch = "arm"),
287+
stable(
288+
feature = "aarch64_neon_crypto_intrinsics",
289+
since = "CURRENT_RUSTC_VERSION"
290+
)
291+
)]
201292
pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
202293
vsha256su0q_u32_(w0_3, w4_7)
203294
}
@@ -209,6 +300,13 @@ pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t
209300
#[target_feature(enable = "sha2")]
210301
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
211302
#[cfg_attr(test, assert_instr(sha256su1))]
303+
#[cfg_attr(
304+
not(target_arch = "arm"),
305+
stable(
306+
feature = "aarch64_neon_crypto_intrinsics",
307+
since = "CURRENT_RUSTC_VERSION"
308+
)
309+
)]
212310
pub unsafe fn vsha256su1q_u32(
213311
tw0_3: uint32x4_t,
214312
w8_11: uint32x4_t,

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