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sayantnAmanieu
sayantn
authored and
Amanieu
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Cleanup: remove redundant target features
Make target feature verification stricter
1 parent 4937369 commit d94f80b

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8 files changed

+71
-48
lines changed

8 files changed

+71
-48
lines changed

‎crates/core_arch/src/x86/avx2.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3137,7 +3137,7 @@ pub unsafe fn _mm256_srlv_epi64(a: __m256i, count: __m256i) -> __m256i {
31373137
///
31383138
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_stream_load_si256)
31393139
#[inline]
3140-
#[target_feature(enable = "avx,avx2")]
3140+
#[target_feature(enable = "avx2")]
31413141
#[cfg_attr(test, assert_instr(vmovntdqa))]
31423142
#[stable(feature = "simd_x86_updates", since = "1.82.0")]
31433143
pub unsafe fn _mm256_stream_load_si256(mem_addr: *const __m256i) -> __m256i {

‎crates/core_arch/src/x86/avx512bf16.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -486,7 +486,7 @@ pub unsafe fn _mm_cvtsbh_ss(a: bf16) -> f32 {
486486
///
487487
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneps_pbh)
488488
#[inline]
489-
#[target_feature(enable = "avx512bf16,avx512vl,sse")]
489+
#[target_feature(enable = "avx512bf16,avx512vl")]
490490
#[cfg_attr(test, assert_instr("vcvtneps2bf16"))]
491491
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
492492
pub unsafe fn _mm_cvtneps_pbh(a: __m128) -> __m128bh {
@@ -506,7 +506,7 @@ pub unsafe fn _mm_cvtneps_pbh(a: __m128) -> __m128bh {
506506
///
507507
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtneps_pbh)
508508
#[inline]
509-
#[target_feature(enable = "avx512bf16,avx512vl,sse,avx512f")]
509+
#[target_feature(enable = "avx512bf16,avx512vl")]
510510
#[cfg_attr(test, assert_instr("vcvtneps2bf16"))]
511511
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
512512
pub unsafe fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh {
@@ -527,7 +527,7 @@ pub unsafe fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m
527527
///
528528
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtneps_pbh)
529529
#[inline]
530-
#[target_feature(enable = "avx512bf16,avx512vl,sse,avx512f")]
530+
#[target_feature(enable = "avx512bf16,avx512vl")]
531531
#[cfg_attr(test, assert_instr("vcvtneps2bf16"))]
532532
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
533533
pub unsafe fn _mm_maskz_cvtneps_pbh(k: __mmask8, a: __m128) -> __m128bh {

‎crates/core_arch/src/x86/avx512f.rs‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -33670,7 +33670,7 @@ pub unsafe fn _mm_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m128d {
3367033670
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_ss)
3367133671
#[inline]
3367233672
#[cfg_attr(test, assert_instr(vmovss))]
33673-
#[target_feature(enable = "sse,avx512f")]
33673+
#[target_feature(enable = "avx512f")]
3367433674
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3367533675
pub unsafe fn _mm_mask_load_ss(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 {
3367633676
let mut dst: __m128 = src;
@@ -33692,7 +33692,7 @@ pub unsafe fn _mm_mask_load_ss(src: __m128, k: __mmask8, mem_addr: *const f32) -
3369233692
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_ss)
3369333693
#[inline]
3369433694
#[cfg_attr(test, assert_instr(vmovss))]
33695-
#[target_feature(enable = "sse,avx512f")]
33695+
#[target_feature(enable = "avx512f")]
3369633696
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3369733697
pub unsafe fn _mm_maskz_load_ss(k: __mmask8, mem_addr: *const f32) -> __m128 {
3369833698
let mut dst: __m128;
@@ -33714,7 +33714,7 @@ pub unsafe fn _mm_maskz_load_ss(k: __mmask8, mem_addr: *const f32) -> __m128 {
3371433714
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_sd)
3371533715
#[inline]
3371633716
#[cfg_attr(test, assert_instr(vmovsd))]
33717-
#[target_feature(enable = "sse,avx512f")]
33717+
#[target_feature(enable = "avx512f")]
3371833718
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3371933719
pub unsafe fn _mm_mask_load_sd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d {
3372033720
let mut dst: __m128d = src;
@@ -33736,7 +33736,7 @@ pub unsafe fn _mm_mask_load_sd(src: __m128d, k: __mmask8, mem_addr: *const f64)
3373633736
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_sd)
3373733737
#[inline]
3373833738
#[cfg_attr(test, assert_instr(vmovsd))]
33739-
#[target_feature(enable = "sse,avx512f")]
33739+
#[target_feature(enable = "avx512f")]
3374033740
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3374133741
pub unsafe fn _mm_maskz_load_sd(k: __mmask8, mem_addr: *const f64) -> __m128d {
3374233742
let mut dst: __m128d;
@@ -34044,7 +34044,7 @@ pub unsafe fn _mm_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d)
3404434044
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_ss)
3404534045
#[inline]
3404634046
#[cfg_attr(test, assert_instr(vmovss))]
34047-
#[target_feature(enable = "sse,avx512f")]
34047+
#[target_feature(enable = "avx512f")]
3404834048
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3404934049
pub unsafe fn _mm_mask_store_ss(mem_addr: *mut f32, k: __mmask8, a: __m128) {
3405034050
asm!(
@@ -34062,7 +34062,7 @@ pub unsafe fn _mm_mask_store_ss(mem_addr: *mut f32, k: __mmask8, a: __m128) {
3406234062
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_sd)
3406334063
#[inline]
3406434064
#[cfg_attr(test, assert_instr(vmovsd))]
34065-
#[target_feature(enable = "sse,avx512f")]
34065+
#[target_feature(enable = "avx512f")]
3406634066
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3406734067
pub unsafe fn _mm_mask_store_sd(mem_addr: *mut f64, k: __mmask8, a: __m128d) {
3406834068
asm!(

‎crates/core_arch/src/x86/avx512fp16.rs‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -667,7 +667,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics
667667
///
668668
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_ph_mask)
669669
#[inline]
670-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,sse")]
670+
#[target_feature(enable = "avx512fp16,avx512vl")]
671671
#[rustc_legacy_const_generics(2)]
672672
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
673673
pub unsafe fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmask8 {
@@ -681,7 +681,7 @@ pub unsafe fn _mm_cmp_ph_mask<const IMM5: i32>(a: __m128h, b: __m128h) -> __mmas
681681
///
682682
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_ph_mask)
683683
#[inline]
684-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,sse")]
684+
#[target_feature(enable = "avx512fp16,avx512vl")]
685685
#[rustc_legacy_const_generics(3)]
686686
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
687687
pub unsafe fn _mm_mask_cmp_ph_mask<const IMM5: i32>(
@@ -698,7 +698,7 @@ pub unsafe fn _mm_mask_cmp_ph_mask<const IMM5: i32>(
698698
///
699699
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_ph_mask)
700700
#[inline]
701-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,avx")]
701+
#[target_feature(enable = "avx512fp16,avx512vl")]
702702
#[rustc_legacy_const_generics(2)]
703703
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
704704
pub unsafe fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __mmask16 {
@@ -712,7 +712,7 @@ pub unsafe fn _mm256_cmp_ph_mask<const IMM5: i32>(a: __m256h, b: __m256h) -> __m
712712
///
713713
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmp_ph_mask)
714714
#[inline]
715-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,avx")]
715+
#[target_feature(enable = "avx512fp16,avx512vl")]
716716
#[rustc_legacy_const_generics(3)]
717717
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
718718
pub unsafe fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
@@ -729,7 +729,7 @@ pub unsafe fn _mm256_mask_cmp_ph_mask<const IMM5: i32>(
729729
///
730730
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_ph_mask)
731731
#[inline]
732-
#[target_feature(enable = "avx512fp16,avx512bw,avx512f")]
732+
#[target_feature(enable = "avx512fp16")]
733733
#[rustc_legacy_const_generics(2)]
734734
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
735735
pub unsafe fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __mmask32 {
@@ -743,7 +743,7 @@ pub unsafe fn _mm512_cmp_ph_mask<const IMM5: i32>(a: __m512h, b: __m512h) -> __m
743743
///
744744
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_ph_mask)
745745
#[inline]
746-
#[target_feature(enable = "avx512fp16,avx512bw,avx512f")]
746+
#[target_feature(enable = "avx512fp16")]
747747
#[rustc_legacy_const_generics(3)]
748748
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
749749
pub unsafe fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
@@ -762,7 +762,7 @@ pub unsafe fn _mm512_mask_cmp_ph_mask<const IMM5: i32>(
762762
///
763763
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_round_ph_mask)
764764
#[inline]
765-
#[target_feature(enable = "avx512fp16,avx512bw,avx512f")]
765+
#[target_feature(enable = "avx512fp16")]
766766
#[rustc_legacy_const_generics(2, 3)]
767767
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
768768
pub unsafe fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
@@ -795,7 +795,7 @@ pub unsafe fn _mm512_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
795795
///
796796
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_round_ph_mask)
797797
#[inline]
798-
#[target_feature(enable = "avx512fp16,avx512bw,avx512f")]
798+
#[target_feature(enable = "avx512fp16")]
799799
#[rustc_legacy_const_generics(3, 4)]
800800
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
801801
pub unsafe fn _mm512_mask_cmp_round_ph_mask<const IMM5: i32, const SAE: i32>(
@@ -1098,7 +1098,7 @@ pub unsafe fn _mm_load_sh(mem_addr: *const f16) -> __m128h {
10981098
///
10991099
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_load_sh)
11001100
#[inline]
1101-
#[target_feature(enable = "avx512fp16,sse,avx512f")]
1101+
#[target_feature(enable = "avx512fp16")]
11021102
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11031103
pub unsafe fn _mm_mask_load_sh(src: __m128h, k: __mmask8, mem_addr: *const f16) -> __m128h {
11041104
let mut dst = src;
@@ -1117,7 +1117,7 @@ pub unsafe fn _mm_mask_load_sh(src: __m128h, k: __mmask8, mem_addr: *const f16)
11171117
///
11181118
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_load_sh)
11191119
#[inline]
1120-
#[target_feature(enable = "avx512fp16,sse,avx512f")]
1120+
#[target_feature(enable = "avx512fp16")]
11211121
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
11221122
pub unsafe fn _mm_maskz_load_sh(k: __mmask8, mem_addr: *const f16) -> __m128h {
11231123
let mut dst: __m128h;
@@ -1255,7 +1255,7 @@ pub unsafe fn _mm_store_sh(mem_addr: *mut f16, a: __m128h) {
12551255
///
12561256
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_store_sh)
12571257
#[inline]
1258-
#[target_feature(enable = "avx512fp16,sse,avx512f")]
1258+
#[target_feature(enable = "avx512fp16")]
12591259
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
12601260
pub unsafe fn _mm_mask_store_sh(mem_addr: *mut f16, k: __mmask8, a: __m128h) {
12611261
asm!(
@@ -11049,7 +11049,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics
1104911049
///
1105011050
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_fpclass_ph_mask)
1105111051
#[inline]
11052-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,sse")]
11052+
#[target_feature(enable = "avx512fp16,avx512vl")]
1105311053
#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
1105411054
#[rustc_legacy_const_generics(1)]
1105511055
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
@@ -11074,7 +11074,7 @@ pub unsafe fn _mm_fpclass_ph_mask<const IMM8: i32>(a: __m128h) -> __mmask8 {
1107411074
///
1107511075
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_fpclass_ph_mask)
1107611076
#[inline]
11077-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,sse")]
11077+
#[target_feature(enable = "avx512fp16,avx512vl")]
1107811078
#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
1107911079
#[rustc_legacy_const_generics(2)]
1108011080
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
@@ -11098,7 +11098,7 @@ pub unsafe fn _mm_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask8, a: __m128h
1109811098
///
1109911099
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_fpclass_ph_mask)
1110011100
#[inline]
11101-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,avx")]
11101+
#[target_feature(enable = "avx512fp16,avx512vl")]
1110211102
#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
1110311103
#[rustc_legacy_const_generics(1)]
1110411104
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
@@ -11123,7 +11123,7 @@ pub unsafe fn _mm256_fpclass_ph_mask<const IMM8: i32>(a: __m256h) -> __mmask16 {
1112311123
///
1112411124
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_fpclass_ph_mask)
1112511125
#[inline]
11126-
#[target_feature(enable = "avx512fp16,avx512vl,avx512f,avx")]
11126+
#[target_feature(enable = "avx512fp16,avx512vl")]
1112711127
#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
1112811128
#[rustc_legacy_const_generics(2)]
1112911129
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
@@ -11147,7 +11147,7 @@ pub unsafe fn _mm256_mask_fpclass_ph_mask<const IMM8: i32>(k1: __mmask16, a: __m
1114711147
///
1114811148
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fpclass_ph_mask)
1114911149
#[inline]
11150-
#[target_feature(enable = "avx512fp16,avx512bw,avx512f")]
11150+
#[target_feature(enable = "avx512fp16")]
1115111151
#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
1115211152
#[rustc_legacy_const_generics(1)]
1115311153
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
@@ -11172,7 +11172,7 @@ pub unsafe fn _mm512_fpclass_ph_mask<const IMM8: i32>(a: __m512h) -> __mmask32 {
1117211172
///
1117311173
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fpclass_ph_mask)
1117411174
#[inline]
11175-
#[target_feature(enable = "avx512fp16,avx512bw,avx512f")]
11175+
#[target_feature(enable = "avx512fp16")]
1117611176
#[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))]
1117711177
#[rustc_legacy_const_generics(2)]
1117811178
#[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]

‎crates/core_arch/src/x86/avxneconvert.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 {
193193
///
194194
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtneps_avx_pbh)
195195
#[inline]
196-
#[target_feature(enable = "avxneconvert,sse")]
196+
#[target_feature(enable = "avxneconvert")]
197197
#[cfg_attr(
198198
all(test, any(target_os = "linux", target_env = "msvc")),
199199
assert_instr(vcvtneps2bf16)
@@ -215,7 +215,7 @@ pub unsafe fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh {
215215
///
216216
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtneps_avx_pbh)
217217
#[inline]
218-
#[target_feature(enable = "avxneconvert,sse,avx")]
218+
#[target_feature(enable = "avxneconvert")]
219219
#[cfg_attr(
220220
all(test, any(target_os = "linux", target_env = "msvc")),
221221
assert_instr(vcvtneps2bf16)

‎crates/core_arch/src/x86/sse2.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1305,7 +1305,7 @@ pub unsafe fn _mm_storel_epi64(mem_addr: *mut __m128i, a: __m128i) {
13051305
///
13061306
/// See [`_mm_sfence`] for details.
13071307
#[inline]
1308-
#[target_feature(enable = "sse,sse2")]
1308+
#[target_feature(enable = "sse2")]
13091309
#[cfg_attr(test, assert_instr(movntdq))]
13101310
#[stable(feature = "simd_x86", since = "1.27.0")]
13111311
pub unsafe fn _mm_stream_si128(mem_addr: *mut __m128i, a: __m128i) {
@@ -2533,7 +2533,7 @@ pub unsafe fn _mm_loadl_pd(a: __m128d, mem_addr: *const f64) -> __m128d {
25332533
///
25342534
/// See [`_mm_sfence`] for details.
25352535
#[inline]
2536-
#[target_feature(enable = "sse,sse2")]
2536+
#[target_feature(enable = "sse2")]
25372537
#[cfg_attr(test, assert_instr(movntpd))]
25382538
#[stable(feature = "simd_x86", since = "1.27.0")]
25392539
#[allow(clippy::cast_ptr_alignment)]

‎crates/core_arch/src/x86/sse41.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1072,7 +1072,7 @@ pub unsafe fn _mm_test_mix_ones_zeros(a: __m128i, mask: __m128i) -> i32 {
10721072
///
10731073
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_stream_load_si128)
10741074
#[inline]
1075-
#[target_feature(enable = "sse,sse4.1")]
1075+
#[target_feature(enable = "sse4.1")]
10761076
#[cfg_attr(test, assert_instr(movntdqa))]
10771077
#[stable(feature = "simd_x86_updates", since = "1.82.0")]
10781078
pub unsafe fn _mm_stream_load_si128(mem_addr: *const __m128i) -> __m128i {

‎crates/stdarch-verify/tests/x86-intel.rs‎

Lines changed: 39 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,7 @@ fn print_missing(map: &HashMap<&str, Vec<&Intrinsic>>, mut f: impl Write) -> io:
405405
f.flush()
406406
}
407407

408-
fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
408+
fn check_target_features(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
409409
// Verify that all `#[target_feature]` annotations are correct,
410410
// ensuring that we've actually enabled the right instruction
411411
// set for this intrinsic.
@@ -432,26 +432,23 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
432432
}
433433
}
434434

435-
let rust_features: HashSet<String> = match rust.target_feature {
435+
let rust_features = match rust.target_feature {
436436
Some(features) => features
437437
.split(',')
438438
.map(|feature| feature.to_string())
439439
.collect(),
440440
None => HashSet::new(),
441441
};
442442

443+
let mut intel_cpuids = HashSet::new();
444+
443445
for cpuid in &intel.cpuid {
444446
// The pause intrinsic is in the SSE2 module, but it is backwards
445447
// compatible with CPUs without SSE2, and it therefore does not need the
446448
// target-feature attribute.
447449
if rust.name == "_mm_pause" {
448450
continue;
449451
}
450-
// this is needed by _xsave and probably some related intrinsics,
451-
// but let's just skip it for now.
452-
if *cpuid == "XSS" {
453-
continue;
454-
}
455452

456453
// these flags on the rdtsc/rtdscp intrinsics we don't test for right
457454
// now, but we may wish to add these one day!
@@ -513,20 +510,46 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
513510
// The XML file names AVX-VNNI_INT16 as "avx_vnni_int16", while Rust calls
514511
// it "avxvnniint16"
515512
"avx_vnni_int16" => String::from("avxvnniint16"),
513+
"xss" => String::from("xsaves"),
516514
_ => cpuid,
517515
};
518-
let fixed_cpuid = fixup_cpuid(cpuid);
519-
520-
if !rust_features.contains(&fixed_cpuid) {
521-
bail!(
522-
"intel cpuid `{}` not in `{:?}` for {}",
523-
fixed_cpuid,
524-
rust_features,
525-
rust.name
526-
);
516+
517+
intel_cpuids.insert(fixup_cpuid(cpuid));
518+
}
519+
520+
if intel_cpuids.contains("gfni") {
521+
if rust.name.contains("mask") {
522+
// LLVM requires avx512bw for all masked GFNI intrinsics, and also avx512vl for the 128- and 256-bit versions
523+
if !rust.name.starts_with("_mm512") {
524+
intel_cpuids.insert(String::from("avx512vl"));
525+
}
526+
intel_cpuids.insert(String::from("avx512bw"));
527+
} else if rust.name.starts_with("_mm256") {
528+
// LLVM requires AVX for all non-masked 256-bit GFNI intrinsics
529+
intel_cpuids.insert(String::from("avx"));
527530
}
528531
}
529532

533+
// Also, 512-bit vpclmulqdq intrisic requires avx512f
534+
if &rust.name == &"_mm512_clmulepi64_epi128" {
535+
intel_cpuids.insert(String::from("avx512f"));
536+
}
537+
538+
if rust_features != intel_cpuids {
539+
bail!(
540+
"Intel cpuids `{:?}` doesn't match Rust `{:?}` for {}",
541+
intel_cpuids,
542+
rust_features,
543+
rust.name
544+
);
545+
}
546+
547+
Ok(())
548+
}
549+
550+
fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> {
551+
check_target_features(rust, intel)?;
552+
530553
if PRINT_INSTRUCTION_VIOLATIONS {
531554
if rust.instrs.is_empty() {
532555
if !intel.instruction.is_empty() && !intel.generates_sequence {

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