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Add #[rustc_legacy_const_generics] to all intrinsics with const-generic parameters
1 parent f48e68d commit cac2005

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7 files changed

+63
-0
lines changed

7 files changed

+63
-0
lines changed

‎crates/core_arch/src/loongarch32/mod.rs‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ unsafe extern "unadjusted" {
1616

1717
/// Generates the cache operation instruction
1818
#[inline]
19+
#[rustc_legacy_const_generics(2)]
1920
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
2021
pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) {
2122
static_assert_simm_bits!(IMM12, 12);
@@ -24,6 +25,7 @@ pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) {
2425

2526
/// Reads the CSR
2627
#[inline]
28+
#[rustc_legacy_const_generics(0)]
2729
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
2830
pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
2931
static_assert_uimm_bits!(IMM14, 14);
@@ -32,6 +34,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
3234

3335
/// Writes the CSR
3436
#[inline]
37+
#[rustc_legacy_const_generics(1)]
3538
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
3639
pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
3740
static_assert_uimm_bits!(IMM14, 14);
@@ -40,6 +43,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
4043

4144
/// Exchanges the CSR
4245
#[inline]
46+
#[rustc_legacy_const_generics(2)]
4347
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
4448
pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
4549
static_assert_uimm_bits!(IMM14, 14);

‎crates/core_arch/src/loongarch64/mod.rs‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ pub fn crcc_w_d_w(a: i64, b: i32) -> i32 {
6363

6464
/// Generates the cache operation instruction
6565
#[inline]
66+
#[rustc_legacy_const_generics(2)]
6667
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
6768
pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) {
6869
static_assert_simm_bits!(IMM12, 12);
@@ -71,6 +72,7 @@ pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) {
7172

7273
/// Reads the CSR
7374
#[inline]
75+
#[rustc_legacy_const_generics(0)]
7476
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
7577
pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
7678
static_assert_uimm_bits!(IMM14, 14);
@@ -79,6 +81,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
7981

8082
/// Writes the CSR
8183
#[inline]
84+
#[rustc_legacy_const_generics(1)]
8285
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
8386
pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
8487
static_assert_uimm_bits!(IMM14, 14);
@@ -87,6 +90,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
8790

8891
/// Exchanges the CSR
8992
#[inline]
93+
#[rustc_legacy_const_generics(2)]
9094
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
9195
pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {
9296
static_assert_uimm_bits!(IMM14, 14);

‎crates/core_arch/src/loongarch_shared/mod.rs‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
114114

115115
/// Generates the memory barrier instruction
116116
#[inline]
117+
#[rustc_legacy_const_generics(0)]
117118
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
118119
pub fn dbar<const IMM15: i32>() {
119120
static_assert_uimm_bits!(IMM15, 15);
@@ -122,6 +123,7 @@ pub fn dbar<const IMM15: i32>() {
122123

123124
/// Generates the instruction-fetch barrier instruction
124125
#[inline]
126+
#[rustc_legacy_const_generics(0)]
125127
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
126128
pub fn ibar<const IMM15: i32>() {
127129
static_assert_uimm_bits!(IMM15, 15);
@@ -130,6 +132,7 @@ pub fn ibar<const IMM15: i32>() {
130132

131133
/// Moves data from a GPR to the FCSR
132134
#[inline]
135+
#[rustc_legacy_const_generics(1)]
133136
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
134137
pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
135138
static_assert_uimm_bits!(IMM5, 5);
@@ -138,6 +141,7 @@ pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
138141

139142
/// Moves data from a FCSR to the GPR
140143
#[inline]
144+
#[rustc_legacy_const_generics(0)]
141145
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
142146
pub fn movfcsr2gr<const IMM5: i32>() -> i32 {
143147
static_assert_uimm_bits!(IMM5, 5);
@@ -188,6 +192,7 @@ pub unsafe fn iocsrwr_w(a: i32, b: i32) {
188192

189193
/// Generates the breakpoint instruction
190194
#[inline]
195+
#[rustc_legacy_const_generics(0)]
191196
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
192197
pub unsafe fn brk<const IMM15: i32>() {
193198
static_assert_uimm_bits!(IMM15, 15);
@@ -203,6 +208,7 @@ pub fn cpucfg(a: i32) -> i32 {
203208

204209
/// Generates the syscall instruction
205210
#[inline]
211+
#[rustc_legacy_const_generics(0)]
206212
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
207213
pub unsafe fn syscall<const IMM15: i32>() {
208214
static_assert_uimm_bits!(IMM15, 15);

‎crates/core_arch/src/powerpc/altivec.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4073,6 +4073,7 @@ where
40734073
/// Vector Convert to Signed Integer
40744074
#[inline]
40754075
#[target_feature(enable = "altivec")]
4076+
#[rustc_legacy_const_generics(1)]
40764077
#[cfg_attr(test, assert_instr(vctsxs, IMM5 = 1))]
40774078
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
40784079
pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
@@ -4084,6 +4085,7 @@ pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
40844085
/// Vector Convert to Unsigned Integer
40854086
#[inline]
40864087
#[target_feature(enable = "altivec")]
4088+
#[rustc_legacy_const_generics(1)]
40874089
#[cfg_attr(test, assert_instr(vctuxs, IMM5 = 1))]
40884090
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
40894091
pub unsafe fn vec_ctu<const IMM5: i32>(a: vector_float) -> vector_unsigned_int {

‎crates/core_arch/src/s390x/vector.rs‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4558,6 +4558,7 @@ pub unsafe fn vec_unpackl<T: sealed::VectorUnpackl>(a: T) -> <T as sealed::Vecto
45584558
/// in the corresponding byte element of d are set to ones. Otherwise, if the bit is zero, the corresponding byte element is set to zero.
45594559
#[inline]
45604560
#[target_feature(enable = "vector")]
4561+
#[rustc_legacy_const_generics(0)]
45614562
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45624563
#[cfg_attr(test, assert_instr(vgbm, MASK = 0x00FF))]
45634564
pub unsafe fn vec_genmask<const MASK: u16>() -> vector_unsigned_char {
@@ -4567,6 +4568,7 @@ pub unsafe fn vec_genmask<const MASK: u16>() -> vector_unsigned_char {
45674568
/// Vector Generate Mask (Byte)
45684569
#[inline]
45694570
#[target_feature(enable = "vector")]
4571+
#[rustc_legacy_const_generics(0, 1)]
45704572
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45714573
#[cfg_attr(test, assert_instr(vrepib, L = 3, H = 5))]
45724574
pub unsafe fn vec_genmasks_8<const L: u8, const H: u8>() -> vector_unsigned_char {
@@ -4576,6 +4578,7 @@ pub unsafe fn vec_genmasks_8<const L: u8, const H: u8>() -> vector_unsigned_char
45764578
/// Vector Generate Mask (Halfword)
45774579
#[inline]
45784580
#[target_feature(enable = "vector")]
4581+
#[rustc_legacy_const_generics(0, 1)]
45794582
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45804583
#[cfg_attr(test, assert_instr(vrepih, L = 3, H = 5))]
45814584
pub unsafe fn vec_genmasks_16<const L: u8, const H: u8>() -> vector_unsigned_short {
@@ -4585,6 +4588,7 @@ pub unsafe fn vec_genmasks_16<const L: u8, const H: u8>() -> vector_unsigned_sho
45854588
/// Vector Generate Mask (Word)
45864589
#[inline]
45874590
#[target_feature(enable = "vector")]
4591+
#[rustc_legacy_const_generics(0, 1)]
45884592
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45894593
#[cfg_attr(test, assert_instr(vgmf, L = 3, H = 5))]
45904594
pub unsafe fn vec_genmasks_32<const L: u8, const H: u8>() -> vector_unsigned_int {
@@ -4594,6 +4598,7 @@ pub unsafe fn vec_genmasks_32<const L: u8, const H: u8>() -> vector_unsigned_int
45944598
/// Vector Generate Mask (Doubleword)
45954599
#[inline]
45964600
#[target_feature(enable = "vector")]
4601+
#[rustc_legacy_const_generics(0, 1)]
45974602
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45984603
#[cfg_attr(test, assert_instr(vgmg, L = 3, H = 5))]
45994604
pub unsafe fn vec_genmasks_64<const L: u8, const H: u8>() -> vector_unsigned_long_long {
@@ -4810,6 +4815,7 @@ pub unsafe fn vec_subec_u128(
48104815
/// Vector Splat Signed Byte
48114816
#[inline]
48124817
#[target_feature(enable = "vector")]
4818+
#[rustc_legacy_const_generics(0)]
48134819
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48144820
#[cfg_attr(test, assert_instr(vrepib, IMM = 42))]
48154821
pub unsafe fn vec_splat_s8<const IMM: i8>() -> vector_signed_char {
@@ -4819,6 +4825,7 @@ pub unsafe fn vec_splat_s8<const IMM: i8>() -> vector_signed_char {
48194825
/// Vector Splat Signed Halfword
48204826
#[inline]
48214827
#[target_feature(enable = "vector")]
4828+
#[rustc_legacy_const_generics(0)]
48224829
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48234830
#[cfg_attr(test, assert_instr(vrepih, IMM = 42))]
48244831
pub unsafe fn vec_splat_s16<const IMM: i16>() -> vector_signed_short {
@@ -4828,6 +4835,7 @@ pub unsafe fn vec_splat_s16<const IMM: i16>() -> vector_signed_short {
48284835
/// Vector Splat Signed Word
48294836
#[inline]
48304837
#[target_feature(enable = "vector")]
4838+
#[rustc_legacy_const_generics(0)]
48314839
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48324840
#[cfg_attr(test, assert_instr(vrepif, IMM = 42))]
48334841
pub unsafe fn vec_splat_s32<const IMM: i16>() -> vector_signed_int {
@@ -4837,6 +4845,7 @@ pub unsafe fn vec_splat_s32<const IMM: i16>() -> vector_signed_int {
48374845
/// Vector Splat Signed Doubleword
48384846
#[inline]
48394847
#[target_feature(enable = "vector")]
4848+
#[rustc_legacy_const_generics(0)]
48404849
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48414850
#[cfg_attr(test, assert_instr(vrepig, IMM = 42))]
48424851
pub unsafe fn vec_splat_s64<const IMM: i16>() -> vector_signed_long_long {
@@ -4846,6 +4855,7 @@ pub unsafe fn vec_splat_s64<const IMM: i16>() -> vector_signed_long_long {
48464855
/// Vector Splat Unsigned Byte
48474856
#[inline]
48484857
#[target_feature(enable = "vector")]
4858+
#[rustc_legacy_const_generics(0)]
48494859
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48504860
#[cfg_attr(test, assert_instr(vrepib, IMM = 42))]
48514861
pub unsafe fn vec_splat_u8<const IMM: u8>() -> vector_unsigned_char {
@@ -4855,6 +4865,7 @@ pub unsafe fn vec_splat_u8<const IMM: u8>() -> vector_unsigned_char {
48554865
/// Vector Splat Unsigned Halfword
48564866
#[inline]
48574867
#[target_feature(enable = "vector")]
4868+
#[rustc_legacy_const_generics(0)]
48584869
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48594870
#[cfg_attr(test, assert_instr(vrepih, IMM = 42))]
48604871
pub unsafe fn vec_splat_u16<const IMM: i16>() -> vector_unsigned_short {
@@ -4864,6 +4875,7 @@ pub unsafe fn vec_splat_u16<const IMM: i16>() -> vector_unsigned_short {
48644875
/// Vector Splat Unsigned Word
48654876
#[inline]
48664877
#[target_feature(enable = "vector")]
4878+
#[rustc_legacy_const_generics(0)]
48674879
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48684880
#[cfg_attr(test, assert_instr(vrepif, IMM = 42))]
48694881
pub unsafe fn vec_splat_u32<const IMM: i16>() -> vector_unsigned_int {
@@ -4873,6 +4885,7 @@ pub unsafe fn vec_splat_u32<const IMM: i16>() -> vector_unsigned_int {
48734885
/// Vector Splat Unsigned Doubleword
48744886
#[inline]
48754887
#[target_feature(enable = "vector")]
4888+
#[rustc_legacy_const_generics(0)]
48764889
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48774890
#[cfg_attr(test, assert_instr(vrepig, IMM = 42))]
48784891
pub unsafe fn vec_splat_u64<const IMM: i16>() -> vector_unsigned_long_long {
@@ -5366,6 +5379,7 @@ pub unsafe fn vec_cp_until_zero_cc<T: sealed::VectorCopyUntilZeroCC>(a: T) -> (T
53665379
/// Vector Multiply Sum Logical
53675380
#[inline]
53685381
#[target_feature(enable = "vector-enhancements-1")]
5382+
#[rustc_legacy_const_generics(3)]
53695383
#[unstable(feature = "stdarch_s390x", issue = "135681")]
53705384
#[cfg_attr(
53715385
all(test, target_feature = "vector-enhancements-1"),

‎crates/core_arch/src/wasm32/mod.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,7 @@ unsafe extern "C-unwind" {
190190
// reenable this attribute.
191191
// #[cfg_attr(test, assert_instr(throw, TAG = 0, ptr = core::ptr::null_mut()))]
192192
#[inline]
193+
#[rustc_legacy_const_generics(1)]
193194
#[unstable(feature = "wasm_exception_handling_intrinsics", issue = "122465")]
194195
// FIXME: Since this instruction unwinds, `core` built with `-C panic=unwind`
195196
// cannot be linked with `-C panic=abort` programs. But that's not

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