@@ -244,6 +244,13 @@ extern "C" {
244244 #[ link_name = "llvm.ppc.altivec.vcmpequw" ]
245245 fn vcmpequw ( a : vector_unsigned_int , b : vector_unsigned_int ) -> vector_bool_int ;
246246
247+ #[ link_name = "llvm.ppc.altivec.vcmpneb" ]
248+ fn vcmpneb ( a : vector_signed_char , b : vector_signed_char ) -> vector_bool_char ;
249+ #[ link_name = "llvm.ppc.altivec.vcmpneh" ]
250+ fn vcmpneh ( a : vector_signed_short , b : vector_signed_short ) -> vector_bool_short ;
251+ #[ link_name = "llvm.ppc.altivec.vcmpnew" ]
252+ fn vcmpnew ( a : vector_signed_int , b : vector_signed_int ) -> vector_bool_int ;
253+
247254 #[ link_name = "llvm.ppc.altivec.vcmpgefp" ]
248255 fn vcmpgefp ( a : vector_float , b : vector_float ) -> vector_bool_int ;
249256
@@ -739,6 +746,34 @@ mod sealed {
739746
740747 impl_vec_cmp ! { [ VectorCmpEq vec_cmpeq] ( vec_vcmpequb, vec_vcmpequh, vec_vcmpequw) }
741748
749+ macro_rules! impl_cmpne {
750+ ( $fun: ident ( $ty: ident) -> $r: ident $( [ $pwr9: ident ] ) ? ) => {
751+ #[ inline]
752+ #[ target_feature( enable = "altivec" ) ]
753+ $( #[ cfg_attr( all( test, target_feature = "power9-altivec" ) , assert_instr( $pwr9) ) ] ) ?
754+ unsafe fn $fun( a: $ty, b: $ty) -> $r {
755+ $( if cfg!( target_feature = "power9-altivec" ) {
756+ transmute( $pwr9( transmute( a) , transmute( b) ) )
757+ } else ) ? {
758+ let zero = transmute( i32x4:: new( 0 , 0 , 0 , 0 ) ) ;
759+ vec_nor( vec_cmpeq( a, b) , zero)
760+ }
761+ }
762+ } ;
763+ }
764+
765+ impl_cmpne ! { vec_vcmpneb( vector_signed_char) -> vector_bool_char [ vcmpneb ] }
766+ impl_cmpne ! { vec_vcmpneh( vector_signed_short) -> vector_bool_short [ vcmpneh ] }
767+ impl_cmpne ! { vec_vcmpnew( vector_signed_int) -> vector_bool_int [ vcmpnew ] }
768+
769+ #[ unstable( feature = "stdarch_powerpc" , issue = "111145" ) ]
770+ pub trait VectorCmpNe < Other > {
771+ type Result ;
772+ unsafe fn vec_cmpne ( self , b : Other ) -> Self :: Result ;
773+ }
774+
775+ impl_vec_cmp ! { [ VectorCmpNe vec_cmpne] ( vec_vcmpneb, vec_vcmpneh, vec_vcmpnew) }
776+
742777 test_impl ! { vec_vcmpbfp( a: vector_float, b: vector_float) -> vector_signed_int [ vcmpbfp, vcmpbfp] }
743778
744779 #[ inline]
@@ -3331,6 +3366,21 @@ where
33313366 a. vec_cmpeq ( b)
33323367}
33333368
3369+ /// Vector Compare Not Equal
3370+ ///
3371+ /// ## Result value
3372+ /// For each element of r, the value of each bit is 1 if the corresponding elements
3373+ /// of a and b are not equal. Otherwise, the value of each bit is 0.
3374+ #[ inline]
3375+ #[ target_feature( enable = "altivec" ) ]
3376+ #[ unstable( feature = "stdarch_powerpc" , issue = "111145" ) ]
3377+ pub unsafe fn vec_cmpne < T , U > ( a : T , b : U ) -> <T as sealed:: VectorCmpNe < U > >:: Result
3378+ where
3379+ T : sealed:: VectorCmpNe < U > ,
3380+ {
3381+ a. vec_cmpne ( b)
3382+ }
3383+
33343384/// Vector cmpb.
33353385#[ inline]
33363386#[ target_feature( enable = "altivec" ) ]
@@ -4317,6 +4367,42 @@ mod tests {
43174367 [ false , true , true , false ]
43184368 }
43194369
4370+ test_vec_2 ! { test_vec_cmpne_i8, vec_cmpne, i8x16 -> m8x16,
4371+ [ 1 , -1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
4372+ [ 0 , 0 , -1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
4373+ [ true , true , true , true , false , false , false , false , false , false , false , false , false , false , false , false ]
4374+ }
4375+
4376+ test_vec_2 ! { test_vec_cmpne_u8, vec_cmpne, u8x16 -> m8x16,
4377+ [ 1 , 255 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
4378+ [ 0 , 0 , 255 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
4379+ [ true , true , true , true , false , false , false , false , false , false , false , false , false , false , false , false ]
4380+ }
4381+
4382+ test_vec_2 ! { test_vec_cmpne_i16, vec_cmpne, i16x8 -> m16x8,
4383+ [ 1 , -1 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
4384+ [ 0 , 0 , -1 , 1 , 0 , 0 , 0 , 0 ] ,
4385+ [ true , true , true , true , false , false , false , false ]
4386+ }
4387+
4388+ test_vec_2 ! { test_vec_cmpne_u16, vec_cmpne, u16x8 -> m16x8,
4389+ [ 1 , 255 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
4390+ [ 0 , 0 , 255 , 1 , 0 , 0 , 0 , 0 ] ,
4391+ [ true , true , true , true , false , false , false , false ]
4392+ }
4393+
4394+ test_vec_2 ! { test_vec_cmpne_i32, vec_cmpne, i32x4 -> m32x4,
4395+ [ 1 , -1 , 0 , 0 ] ,
4396+ [ 0 , -1 , 0 , 1 ] ,
4397+ [ true , false , false , true ]
4398+ }
4399+
4400+ test_vec_2 ! { test_vec_cmpne_u32, vec_cmpne, u32x4 -> m32x4,
4401+ [ 1 , 255 , 0 , 0 ] ,
4402+ [ 0 , 255 , 0 , 1 ] ,
4403+ [ true , false , false , true ]
4404+ }
4405+
43204406 test_vec_2 ! { test_vec_all_eq_i8_false, vec_all_eq, i8x16 -> bool ,
43214407 [ 1 , -1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
43224408 [ 0 , 0 , -1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] ,
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