add #[target_feature(enable = ...)]

Author: japaric

coresimd/arm/cmsis.rs

@@ -10,7 +10,8 @@
 ///
 /// Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be
 /// executed in Privileged modes.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __enable_irq() {
     asm!("cpsie i" : : : "memory" : "volatile");
 }
@@ -19,15 +20,17 @@ pub unsafe fn __enable_irq() {
 ///
 /// Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be
 /// executed in Privileged modes.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __disable_irq() {
     asm!("cpsid i" : : : "memory" : "volatile");
 }
 
 /// Get Control Register
 ///
 /// Returns the content of the Control Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_CONTROL() -> u32 {
     let result: u32;
     asm!("mrs $0, CONTROL" : "=r"(result) : : : "volatile");
@@ -37,15 +40,17 @@ pub unsafe fn __get_CONTROL() -> u32 {
 /// Set Control Register
 ///
 /// Writes the given value to the Control Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __set_CONTROL(control: u32) {
     asm!("msr CONTROL, $0" : : "r"(control) : "memory" : "volatile");
 }
 
 /// Get IPSR Register
 ///
 /// Returns the content of the IPSR Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_IPSR() -> u32 {
     let result: u32;
     asm!("mrs $0, IPSR" : "=r"(result) : : : "volatile");
@@ -55,7 +60,8 @@ pub unsafe fn __get_IPSR() -> u32 {
 /// Get APSR Register
 ///
 /// Returns the content of the APSR Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_APSR() -> u32 {
     let result: u32;
     asm!("mrs $0, APSR" : "=r"(result) : : : "volatile");
@@ -65,7 +71,8 @@ pub unsafe fn __get_APSR() -> u32 {
 /// Get xPSR Register
 ///
 /// Returns the content of the xPSR Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_xPSR() -> u32 {
     let result: u32;
     asm!("mrs $0, XPSR" : "=r"(result) : : : "volatile");
@@ -75,7 +82,8 @@ pub unsafe fn __get_xPSR() -> u32 {
 /// Get Process Stack Pointer
 ///
 /// Returns the current value of the Process Stack Pointer (PSP).
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_PSP() -> u32 {
     let result: u32;
     asm!("mrs $0, PSP" : "=r"(result) : : : "volatile");
@@ -85,15 +93,17 @@ pub unsafe fn __get_PSP() -> u32 {
 /// Set Process Stack Pointer
 ///
 /// Assigns the given value to the Process Stack Pointer (PSP).
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __set_PSP(top_of_proc_stack: u32) {
     asm!("msr PSP, $0" : : "r"(top_of_proc_stack) : : "volatile");
 }
 
 /// Get Main Stack Pointer
 ///
 /// Returns the current value of the Main Stack Pointer (MSP).
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_MSP() -> u32 {
     let result: u32;
     asm!("mrs $0, MSP" : "=r"(result) : : : "volatile");
@@ -103,7 +113,8 @@ pub unsafe fn __get_MSP() -> u32 {
 /// Set Main Stack Pointer
 ///
 /// Assigns the given value to the Main Stack Pointer (MSP).
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __set_MSP(top_of_main_stack: u32) {
     asm!("msr MSP, $0" : : "r"(top_of_main_stack) : : "volatile");
 }
@@ -112,7 +123,8 @@ pub unsafe fn __set_MSP(top_of_main_stack: u32) {
 ///
 /// Returns the current state of the priority mask bit from the Priority Mask
 /// Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __get_PRIMASK() -> u32 {
     let result: u32;
     asm!("mrs $0, PRIMASK" : "=r"(result) : : "memory" : "volatile");
@@ -122,7 +134,8 @@ pub unsafe fn __get_PRIMASK() -> u32 {
 /// Set Priority Mask
 ///
 /// Assigns the given value to the Priority Mask Register.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __set_PRIMASK(pri_mask: u32) {
     asm!("msr PRIMASK, $0" : : "r"(pri_mask) : : "volatile");
 }
@@ -133,7 +146,8 @@ mod v7 {
     ///
     /// Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be
     /// executed in Privileged modes.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __enable_fault_irq() {
         asm!("cpsie f" : : : "memory" : "volatile");
     }
@@ -142,15 +156,17 @@ mod v7 {
     ///
     /// Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be
     /// executed in Privileged modes.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __disable_fault_irq() {
         asm!("cpsid f" : : : "memory" : "volatile");
     }
 
     /// Get Base Priority
     ///
     /// Returns the current value of the Base Priority register.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __get_BASEPRI() -> u32 {
         let result: u32;
         asm!("mrs $0, BASEPRI" : "=r"(result) : : : "volatile");
@@ -160,7 +176,8 @@ mod v7 {
     /// Set Base Priority
     ///
     /// Assigns the given value to the Base Priority register.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __set_BASEPRI(base_pri: u32) {
         asm!("msr BASEPRI, $0" : : "r"(base_pri) : "memory" : "volatile");
     }
@@ -170,15 +187,17 @@ mod v7 {
     /// Assigns the given value to the Base Priority register only if BASEPRI
     /// masking is disabled, or the new value increases the BASEPRI
     /// priority level.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __set_BASEPRI_MAX(base_pri: u32) {
         asm!("msr BASEPRI_MAX, $0" : : "r"(base_pri) : "memory" : "volatile");
     }
 
     /// Get Fault Mask
     ///
     /// Returns the current value of the Fault Mask register.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __get_FAULTMASK() -> u32 {
         let result: u32;
         asm!("mrs $0, FAULTMASK" : "=r"(result) : : : "volatile");
@@ -188,7 +207,8 @@ mod v7 {
     /// Set Fault Mask
     ///
     /// Assigns the given value to the Fault Mask register.
-    #[inline(always)]
+    #[inline]
+    #[target_feature(enable = "mclass")]
     pub unsafe fn __set_FAULTMASK(fault_mask: u32) {
         asm!("msr FAULTMASK, $0" : : "r"(fault_mask) : "memory" : "volatile");
     }
@@ -203,7 +223,8 @@ pub use self::v7::*;
 ///
 /// No Operation does nothing. This instruction can be used for code alignment
 /// purposes.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __NOP() {
     asm!("nop" : : : : "volatile");
 }
@@ -212,7 +233,8 @@ pub unsafe fn __NOP() {
 ///
 /// Wait For Interrupt is a hint instruction that suspends execution until one
 /// of a number of events occurs.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __WFI() {
     asm!("wfi" : : : : "volatile");
 }
@@ -221,7 +243,8 @@ pub unsafe fn __WFI() {
 ///
 /// Wait For Event is a hint instruction that permits the processor to enter a
 /// low-power state until one of a number of events occurs.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __WFE() {
     asm!("wfe" : : : : "volatile");
 }
@@ -230,7 +253,8 @@ pub unsafe fn __WFE() {
 ///
 /// Send Event is a hint instruction. It causes an event to be signaled to the
 /// CPU.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __SEV() {
     asm!("sev" : : : : "volatile");
 }
@@ -240,7 +264,8 @@ pub unsafe fn __SEV() {
 /// Instruction Synchronization Barrier flushes the pipeline in the processor,
 /// so that all instructions following the ISB are fetched from cache or
 /// memory, after the instruction has been completed.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __ISB() {
     asm!("isb 0xF" : : : "memory" : "volatile");
 }
@@ -249,7 +274,8 @@ pub unsafe fn __ISB() {
 ///
 /// Acts as a special kind of Data Memory Barrier. It completes when all
 /// explicit memory accesses before this instruction complete.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __DSB() {
     asm!("dsb 0xF" : : : "memory" : "volatile");
 }
@@ -258,7 +284,8 @@ pub unsafe fn __DSB() {
 ///
 /// Ensures the apparent order of the explicit memory operations before and
 /// after the instruction, without ensuring their completion.
-#[inline(always)]
+#[inline]
+#[target_feature(enable = "mclass")]
 pub unsafe fn __DMB() {
     asm!("dmb 0xF" : : : "memory" : "volatile");
 }