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sayantnAmanieu
sayantn
authored and
Amanieu
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Fix CI errors due to alignment issues in msvc
1 parent e907456 commit 4c92345

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4 files changed

+142
-35
lines changed

4 files changed

+142
-35
lines changed

‎crates/core_arch/src/x86/avx.rs‎

Lines changed: 24 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1425,7 +1425,10 @@ pub fn _mm256_insert_epi32<const INDEX: i32>(a: __m256i, i: i32) -> __m256i {
14251425
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_pd)
14261426
#[inline]
14271427
#[target_feature(enable = "avx")]
1428-
#[cfg_attr(test, assert_instr(vmovap))]
1428+
#[cfg_attr(
1429+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1430+
assert_instr(vmovap)
1431+
)]
14291432
#[stable(feature = "simd_x86", since = "1.27.0")]
14301433
#[allow(clippy::cast_ptr_alignment)]
14311434
pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
@@ -1440,7 +1443,10 @@ pub unsafe fn _mm256_load_pd(mem_addr: *const f64) -> __m256d {
14401443
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_pd)
14411444
#[inline]
14421445
#[target_feature(enable = "avx")]
1443-
#[cfg_attr(test, assert_instr(vmovap))]
1446+
#[cfg_attr(
1447+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1448+
assert_instr(vmovap)
1449+
)]
14441450
#[stable(feature = "simd_x86", since = "1.27.0")]
14451451
#[allow(clippy::cast_ptr_alignment)]
14461452
pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
@@ -1455,7 +1461,10 @@ pub unsafe fn _mm256_store_pd(mem_addr: *mut f64, a: __m256d) {
14551461
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_ps)
14561462
#[inline]
14571463
#[target_feature(enable = "avx")]
1458-
#[cfg_attr(test, assert_instr(vmovaps))]
1464+
#[cfg_attr(
1465+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1466+
assert_instr(vmovaps)
1467+
)]
14591468
#[stable(feature = "simd_x86", since = "1.27.0")]
14601469
#[allow(clippy::cast_ptr_alignment)]
14611470
pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
@@ -1470,7 +1479,10 @@ pub unsafe fn _mm256_load_ps(mem_addr: *const f32) -> __m256 {
14701479
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_ps)
14711480
#[inline]
14721481
#[target_feature(enable = "avx")]
1473-
#[cfg_attr(test, assert_instr(vmovaps))]
1482+
#[cfg_attr(
1483+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1484+
assert_instr(vmovaps)
1485+
)]
14741486
#[stable(feature = "simd_x86", since = "1.27.0")]
14751487
#[allow(clippy::cast_ptr_alignment)]
14761488
pub unsafe fn _mm256_store_ps(mem_addr: *mut f32, a: __m256) {
@@ -1548,7 +1560,10 @@ pub unsafe fn _mm256_storeu_ps(mem_addr: *mut f32, a: __m256) {
15481560
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_si256)
15491561
#[inline]
15501562
#[target_feature(enable = "avx")]
1551-
#[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovdqa expected
1563+
#[cfg_attr(
1564+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1565+
assert_instr(vmovaps)
1566+
)] // FIXME vmovdqa expected
15521567
#[stable(feature = "simd_x86", since = "1.27.0")]
15531568
pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
15541569
*mem_addr
@@ -1561,7 +1576,10 @@ pub unsafe fn _mm256_load_si256(mem_addr: *const __m256i) -> __m256i {
15611576
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_si256)
15621577
#[inline]
15631578
#[target_feature(enable = "avx")]
1564-
#[cfg_attr(test, assert_instr(vmovaps))] // FIXME vmovdqa expected
1579+
#[cfg_attr(
1580+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1581+
assert_instr(vmovaps)
1582+
)] // FIXME vmovdqa expected
15651583
#[stable(feature = "simd_x86", since = "1.27.0")]
15661584
pub unsafe fn _mm256_store_si256(mem_addr: *mut __m256i, a: __m256i) {
15671585
*mem_addr = a;

‎crates/core_arch/src/x86/avx512f.rs‎

Lines changed: 72 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -34468,7 +34468,10 @@ pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) {
3446834468
#[inline]
3446934469
#[target_feature(enable = "avx512f")]
3447034470
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34471-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34471+
#[cfg_attr(
34472+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34473+
assert_instr(vmovaps)
34474+
)] //should be vmovdqa32
3447234475
pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
3447334476
ptr::read(mem_addr)
3447434477
}
@@ -34479,7 +34482,10 @@ pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i {
3447934482
#[inline]
3448034483
#[target_feature(enable = "avx512f")]
3448134484
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34482-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34485+
#[cfg_attr(
34486+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34487+
assert_instr(vmovaps)
34488+
)] //should be vmovdqa32
3448334489
pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
3448434490
ptr::write(mem_addr, a);
3448534491
}
@@ -34490,7 +34496,10 @@ pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) {
3449034496
#[inline]
3449134497
#[target_feature(enable = "avx512f")]
3449234498
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34493-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34499+
#[cfg_attr(
34500+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34501+
assert_instr(vmovaps)
34502+
)] //should be vmovdqa32
3449434503
pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
3449534504
ptr::read(mem_addr as *const __m512i)
3449634505
}
@@ -34501,7 +34510,10 @@ pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i {
3450134510
#[inline]
3450234511
#[target_feature(enable = "avx512f,avx512vl")]
3450334512
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34504-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34513+
#[cfg_attr(
34514+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34515+
assert_instr(vmovaps)
34516+
)] //should be vmovdqa32
3450534517
pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
3450634518
ptr::read(mem_addr as *const __m256i)
3450734519
}
@@ -34512,7 +34524,10 @@ pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i {
3451234524
#[inline]
3451334525
#[target_feature(enable = "avx512f,avx512vl")]
3451434526
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34515-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34527+
#[cfg_attr(
34528+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34529+
assert_instr(vmovaps)
34530+
)] //should be vmovdqa32
3451634531
pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
3451734532
ptr::read(mem_addr as *const __m128i)
3451834533
}
@@ -34523,7 +34538,10 @@ pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i {
3452334538
#[inline]
3452434539
#[target_feature(enable = "avx512f")]
3452534540
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34526-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34541+
#[cfg_attr(
34542+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34543+
assert_instr(vmovaps)
34544+
)] //should be vmovdqa32
3452734545
pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
3452834546
ptr::write(mem_addr as *mut __m512i, a);
3452934547
}
@@ -34534,7 +34552,10 @@ pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) {
3453434552
#[inline]
3453534553
#[target_feature(enable = "avx512f,avx512vl")]
3453634554
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34537-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34555+
#[cfg_attr(
34556+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34557+
assert_instr(vmovaps)
34558+
)] //should be vmovdqa32
3453834559
pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
3453934560
ptr::write(mem_addr as *mut __m256i, a);
3454034561
}
@@ -34545,7 +34566,10 @@ pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) {
3454534566
#[inline]
3454634567
#[target_feature(enable = "avx512f,avx512vl")]
3454734568
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34548-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa32
34569+
#[cfg_attr(
34570+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34571+
assert_instr(vmovaps)
34572+
)] //should be vmovdqa32
3454934573
pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
3455034574
ptr::write(mem_addr as *mut __m128i, a);
3455134575
}
@@ -34556,7 +34580,10 @@ pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) {
3455634580
#[inline]
3455734581
#[target_feature(enable = "avx512f")]
3455834582
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34559-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34583+
#[cfg_attr(
34584+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34585+
assert_instr(vmovaps)
34586+
)] //should be vmovdqa64
3456034587
pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
3456134588
ptr::read(mem_addr as *const __m512i)
3456234589
}
@@ -34567,7 +34594,10 @@ pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i {
3456734594
#[inline]
3456834595
#[target_feature(enable = "avx512f,avx512vl")]
3456934596
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34570-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34597+
#[cfg_attr(
34598+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34599+
assert_instr(vmovaps)
34600+
)] //should be vmovdqa64
3457134601
pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
3457234602
ptr::read(mem_addr as *const __m256i)
3457334603
}
@@ -34578,7 +34608,10 @@ pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i {
3457834608
#[inline]
3457934609
#[target_feature(enable = "avx512f,avx512vl")]
3458034610
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34581-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34611+
#[cfg_attr(
34612+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34613+
assert_instr(vmovaps)
34614+
)] //should be vmovdqa64
3458234615
pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
3458334616
ptr::read(mem_addr as *const __m128i)
3458434617
}
@@ -34589,7 +34622,10 @@ pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i {
3458934622
#[inline]
3459034623
#[target_feature(enable = "avx512f")]
3459134624
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34592-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34625+
#[cfg_attr(
34626+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34627+
assert_instr(vmovaps)
34628+
)] //should be vmovdqa64
3459334629
pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
3459434630
ptr::write(mem_addr as *mut __m512i, a);
3459534631
}
@@ -34600,7 +34636,10 @@ pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) {
3460034636
#[inline]
3460134637
#[target_feature(enable = "avx512f,avx512vl")]
3460234638
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34603-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34639+
#[cfg_attr(
34640+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34641+
assert_instr(vmovaps)
34642+
)] //should be vmovdqa64
3460434643
pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
3460534644
ptr::write(mem_addr as *mut __m256i, a);
3460634645
}
@@ -34611,7 +34650,10 @@ pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) {
3461134650
#[inline]
3461234651
#[target_feature(enable = "avx512f,avx512vl")]
3461334652
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34614-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovdqa64
34653+
#[cfg_attr(
34654+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34655+
assert_instr(vmovaps)
34656+
)] //should be vmovdqa64
3461534657
pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
3461634658
ptr::write(mem_addr as *mut __m128i, a);
3461734659
}
@@ -34622,7 +34664,10 @@ pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) {
3462234664
#[inline]
3462334665
#[target_feature(enable = "avx512f")]
3462434666
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34625-
#[cfg_attr(test, assert_instr(vmovaps))]
34667+
#[cfg_attr(
34668+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34669+
assert_instr(vmovaps)
34670+
)]
3462634671
pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
3462734672
ptr::read(mem_addr as *const __m512)
3462834673
}
@@ -34633,7 +34678,10 @@ pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 {
3463334678
#[inline]
3463434679
#[target_feature(enable = "avx512f")]
3463534680
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34636-
#[cfg_attr(test, assert_instr(vmovaps))]
34681+
#[cfg_attr(
34682+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34683+
assert_instr(vmovaps)
34684+
)]
3463734685
pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
3463834686
ptr::write(mem_addr as *mut __m512, a);
3463934687
}
@@ -34644,7 +34692,10 @@ pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) {
3464434692
#[inline]
3464534693
#[target_feature(enable = "avx512f")]
3464634694
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34647-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovapd
34695+
#[cfg_attr(
34696+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34697+
assert_instr(vmovaps)
34698+
)] //should be vmovapd
3464834699
pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
3464934700
ptr::read(mem_addr as *const __m512d)
3465034701
}
@@ -34655,7 +34706,10 @@ pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d {
3465534706
#[inline]
3465634707
#[target_feature(enable = "avx512f")]
3465734708
#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
34658-
#[cfg_attr(test, assert_instr(vmovaps))] //should be vmovapd
34709+
#[cfg_attr(
34710+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
34711+
assert_instr(vmovaps)
34712+
)] //should be vmovapd
3465934713
pub unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) {
3466034714
ptr::write(mem_addr as *mut __m512d, a);
3466134715
}

‎crates/core_arch/src/x86/sse.rs‎

Lines changed: 26 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1158,7 +1158,12 @@ pub unsafe fn _mm_load_ps1(p: *const f32) -> __m128 {
11581158
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_ps)
11591159
#[inline]
11601160
#[target_feature(enable = "sse")]
1161-
#[cfg_attr(test, assert_instr(movaps))]
1161+
// FIXME: Rust doesn't emit alignment attributes for MSVC x86-32. Ref https://github.com/rust-lang/rust/pull/139261
1162+
// All aligned load/store intrinsics are affected
1163+
#[cfg_attr(
1164+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1165+
assert_instr(movaps)
1166+
)]
11621167
#[stable(feature = "simd_x86", since = "1.27.0")]
11631168
#[allow(clippy::cast_ptr_alignment)]
11641169
pub unsafe fn _mm_load_ps(p: *const f32) -> __m128 {
@@ -1213,7 +1218,10 @@ pub unsafe fn _mm_loadu_ps(p: *const f32) -> __m128 {
12131218
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadr_ps)
12141219
#[inline]
12151220
#[target_feature(enable = "sse")]
1216-
#[cfg_attr(test, assert_instr(movaps))]
1221+
#[cfg_attr(
1222+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1223+
assert_instr(movaps)
1224+
)]
12171225
#[stable(feature = "simd_x86", since = "1.27.0")]
12181226
pub unsafe fn _mm_loadr_ps(p: *const f32) -> __m128 {
12191227
let a = _mm_load_ps(p);
@@ -1253,7 +1261,10 @@ pub unsafe fn _mm_store_ss(p: *mut f32, a: __m128) {
12531261
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store1_ps)
12541262
#[inline]
12551263
#[target_feature(enable = "sse")]
1256-
#[cfg_attr(test, assert_instr(movaps))]
1264+
#[cfg_attr(
1265+
all(test, not(all(target_arch = "x86", target_env = "msvc"))),
1266+
assert_instr(movaps)
1267+
)]
12571268
#[stable(feature = "simd_x86", since = "1.27.0")]
12581269
#[allow(clippy::cast_ptr_alignment)]
12591270
pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
@@ -1266,7 +1277,10 @@ pub unsafe fn _mm_store1_ps(p: *mut f32, a: __m128) {
12661277
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_ps1)
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#[inline]
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#[target_feature(enable = "sse")]
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#[cfg_attr(test, assert_instr(movaps))]
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#[cfg_attr(
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all(test, not(all(target_arch = "x86", target_env = "msvc"))),
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assert_instr(movaps)
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)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
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_mm_store1_ps(p, a);
@@ -1285,7 +1299,10 @@ pub unsafe fn _mm_store_ps1(p: *mut f32, a: __m128) {
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/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_ps)
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#[inline]
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#[target_feature(enable = "sse")]
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#[cfg_attr(test, assert_instr(movaps))]
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#[cfg_attr(
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all(test, not(all(target_arch = "x86", target_env = "msvc"))),
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assert_instr(movaps)
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)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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#[allow(clippy::cast_ptr_alignment)]
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pub unsafe fn _mm_store_ps(p: *mut f32, a: __m128) {
@@ -1329,7 +1346,10 @@ pub unsafe fn _mm_storeu_ps(p: *mut f32, a: __m128) {
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/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storer_ps)
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#[inline]
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#[target_feature(enable = "sse")]
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#[cfg_attr(test, assert_instr(movaps))]
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#[cfg_attr(
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all(test, not(all(target_arch = "x86", target_env = "msvc"))),
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assert_instr(movaps)
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)]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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#[allow(clippy::cast_ptr_alignment)]
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pub unsafe fn _mm_storer_ps(p: *mut f32, a: __m128) {

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