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lines changed

5 files changed

+29
-29
lines changed

‎coresimd/powerpc/altivec.rs‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -526,19 +526,19 @@ mod sealed {
526526
}
527527
}
528528

529-
vector_perm!{ vector_signed_char }
530-
vector_perm!{ vector_unsigned_char }
531-
vector_perm!{ vector_bool_char }
529+
vector_perm! { vector_signed_char }
530+
vector_perm! { vector_unsigned_char }
531+
vector_perm! { vector_bool_char }
532532

533-
vector_perm!{ vector_signed_short }
534-
vector_perm!{ vector_unsigned_short }
535-
vector_perm!{ vector_bool_short }
533+
vector_perm! { vector_signed_short }
534+
vector_perm! { vector_unsigned_short }
535+
vector_perm! { vector_bool_short }
536536

537-
vector_perm!{ vector_signed_int }
538-
vector_perm!{ vector_unsigned_int }
539-
vector_perm!{ vector_bool_int }
537+
vector_perm! { vector_signed_int }
538+
vector_perm! { vector_unsigned_int }
539+
vector_perm! { vector_bool_int }
540540

541-
vector_perm!{ vector_float }
541+
vector_perm! { vector_float }
542542

543543
pub trait VectorAdd<Other> {
544544
type Result;
@@ -1085,72 +1085,72 @@ mod tests {
10851085
}
10861086
}
10871087

1088-
test_vec_perm!{test_vec_perm_u8x16,
1088+
test_vec_perm! {test_vec_perm_u8x16,
10891089
u8x16, vector_unsigned_char,
10901090
[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
10911091
[100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
10921092
[0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
10931093
0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
10941094
[0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
1095-
test_vec_perm!{test_vec_perm_i8x16,
1095+
test_vec_perm! {test_vec_perm_i8x16,
10961096
i8x16, vector_signed_char,
10971097
[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
10981098
[100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115],
10991099
[0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
11001100
0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
11011101
[0, 1, 100, 101, 2, 3, 102, 103, 4, 5, 104, 105, 6, 7, 106, 107]}
11021102

1103-
test_vec_perm!{test_vec_perm_m8x16,
1103+
test_vec_perm! {test_vec_perm_m8x16,
11041104
m8x16, vector_bool_char,
11051105
[false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false],
11061106
[true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true],
11071107
[0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
11081108
0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
11091109
[false, false, true, true, false, false, true, true, false, false, true, true, false, false, true, true]}
1110-
test_vec_perm!{test_vec_perm_u16x8,
1110+
test_vec_perm! {test_vec_perm_u16x8,
11111111
u16x8, vector_unsigned_short,
11121112
[0, 1, 2, 3, 4, 5, 6, 7],
11131113
[10, 11, 12, 13, 14, 15, 16, 17],
11141114
[0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
11151115
0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
11161116
[0, 10, 1, 11, 2, 12, 3, 13]}
1117-
test_vec_perm!{test_vec_perm_i16x8,
1117+
test_vec_perm! {test_vec_perm_i16x8,
11181118
i16x8, vector_signed_short,
11191119
[0, 1, 2, 3, 4, 5, 6, 7],
11201120
[10, 11, 12, 13, 14, 15, 16, 17],
11211121
[0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
11221122
0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
11231123
[0, 10, 1, 11, 2, 12, 3, 13]}
1124-
test_vec_perm!{test_vec_perm_m16x8,
1124+
test_vec_perm! {test_vec_perm_m16x8,
11251125
m16x8, vector_bool_short,
11261126
[false, false, false, false, false, false, false, false],
11271127
[true, true, true, true, true, true, true, true],
11281128
[0x00, 0x01, 0x10, 0x11, 0x02, 0x03, 0x12, 0x13,
11291129
0x04, 0x05, 0x14, 0x15, 0x06, 0x07, 0x16, 0x17],
11301130
[false, true, false, true, false, true, false, true]}
11311131

1132-
test_vec_perm!{test_vec_perm_u32x4,
1132+
test_vec_perm! {test_vec_perm_u32x4,
11331133
u32x4, vector_unsigned_int,
11341134
[0, 1, 2, 3],
11351135
[10, 11, 12, 13],
11361136
[0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
11371137
0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
11381138
[0, 10, 1, 11]}
1139-
test_vec_perm!{test_vec_perm_i32x4,
1139+
test_vec_perm! {test_vec_perm_i32x4,
11401140
i32x4, vector_signed_int,
11411141
[0, 1, 2, 3],
11421142
[10, 11, 12, 13],
11431143
[0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
11441144
0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
11451145
[0, 10, 1, 11]}
1146-
test_vec_perm!{test_vec_perm_m32x4,
1146+
test_vec_perm! {test_vec_perm_m32x4,
11471147
m32x4, vector_bool_int,
11481148
[false, false, false, false],
11491149
[true, true, true, true],
11501150
[0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
11511151
0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17],
11521152
[false, true, false, true]}
1153-
test_vec_perm!{test_vec_perm_f32x4,
1153+
test_vec_perm! {test_vec_perm_f32x4,
11541154
f32x4, vector_float,
11551155
[0.0, 1.0, 2.0, 3.0],
11561156
[1.0, 1.1, 1.2, 1.3],

‎coresimd/powerpc/vsx.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,8 @@ mod tests {
115115
}
116116
}
117117

118-
test_vec_xxpermdi!{test_vec_xxpermdi_u64x2, u64x2, vector_unsigned_long, [0], [1], [2], [3]}
119-
test_vec_xxpermdi!{test_vec_xxpermdi_i64x2, i64x2, vector_signed_long, [0], [-1], [2], [-3]}
120-
test_vec_xxpermdi!{test_vec_xxpermdi_m64x2, m64x2, vector_bool_long, [false], [true], [false], [true]}
121-
test_vec_xxpermdi!{test_vec_xxpermdi_f64x2, f64x2, vector_double, [0.0], [1.0], [2.0], [3.0]}
118+
test_vec_xxpermdi! {test_vec_xxpermdi_u64x2, u64x2, vector_unsigned_long, [0], [1], [2], [3]}
119+
test_vec_xxpermdi! {test_vec_xxpermdi_i64x2, i64x2, vector_signed_long, [0], [-1], [2], [-3]}
120+
test_vec_xxpermdi! {test_vec_xxpermdi_m64x2, m64x2, vector_bool_long, [false], [true], [false], [true]}
121+
test_vec_xxpermdi! {test_vec_xxpermdi_f64x2, f64x2, vector_double, [0.0], [1.0], [2.0], [3.0]}
122122
}

‎coresimd/x86/tbm.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -288,7 +288,7 @@ mod tests {
288288
unsafe fn test_bextr_u32() {
289289
assert_eq!(_bextr_u32(0b0101_0000u32, 4, 4), 0b0000_0101u32);
290290
}
291-
291+
292292
#[simd_test(enable = "tbm")]
293293
unsafe fn test_bextr_u64() {
294294
assert_eq!(_bextr_u64(0b0101_0000u64, 4, 4), 0b0000_0101u64);

‎coresimd/x86/xsave.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ mod tests {
218218
let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
219219
let mut a = XsaveArea::new();
220220
let mut b = XsaveArea::new();
221-
221+
222222
_xsave(a.ptr(), m);
223223
_xrstor(a.ptr(), m);
224224
_xsave(b.ptr(), m);
@@ -246,7 +246,7 @@ mod tests {
246246
let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
247247
let mut a = XsaveArea::new();
248248
let mut b = XsaveArea::new();
249-
249+
250250
_xsaveopt(a.ptr(), m);
251251
_xrstor(a.ptr(), m);
252252
_xsaveopt(b.ptr(), m);
@@ -275,7 +275,7 @@ mod tests {
275275
let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
276276
let mut a = XsaveArea::new();
277277
let mut b = XsaveArea::new();
278-
278+
279279
_xsaves(a.ptr(), m);
280280
_xrstors(a.ptr(), m);
281281
_xsaves(b.ptr(), m);

‎crates/simd-test-macro/src/lib.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ pub fn simd_test(
9191
};
9292
q.to_tokens(&mut cfg_target_features);
9393
}
94-
let q = quote!{ true };
94+
let q = quote! { true };
9595
q.to_tokens(&mut cfg_target_features);
9696

9797
let test_norun = std::env::var("STDSIMD_TEST_NORUN").is_ok();

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