@@ -146,24 +146,25 @@ pub unsafe fn _mm_blend_ps<const IMM4: i32>(a: __m128, b: __m128) -> __m128 {
146146///
147147/// # Example
148148/// ```rust
149- /// #[cfg(target_arch = "x86")]
150- /// #use std::arch::x86::*;
151- /// #[cfg(target_arch = "x86_64")]
152- /// #use std::arch::x86_64::*;
153- /// #fn main() {
149+ /// # # [cfg(target_arch = "x86")]
150+ /// # use std::arch::x86::*;
151+ /// # # [cfg(target_arch = "x86_64")]
152+ /// # use std::arch::x86_64::*;
153+ /// # fn main() {
154154/// # if is_x86_feature_detected!("sse4.1") {
155- /// # #[target_feature(enable = "sse4.1")]
156- /// # unsafe fn worker() {
155+ /// # #[target_feature(enable = "sse4.1")]
156+ /// # unsafe fn worker() {
157157/// let mut float_store = vec![1.0, 1.0, 2.0, 3.0];
158158/// unsafe {
159159/// let simd_floats = _mm_set_ps(2.5, 5.0, 7.5, 10.0);
160160/// let x: i32 = _mm_extract_ps::<2>(simd_floats);
161161/// float_store.push(f32::from_bits(x as u32));
162162/// }
163163/// assert_eq!(float_store, vec![1.0, 1.0, 2.0, 3.0, 5.0]);
164- /// # }
165- /// # unsafe { worker() }
166- /// #}
164+ /// # }
165+ /// # unsafe { worker() }
166+ /// # }
167+ /// # }
167168/// ```
168169/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_ps)
169170#[ inline]
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