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Add #[rustc_legacy_const_generics] to all intrinsics with const-generic parameters
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8 files changed

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‎crates/core_arch/src/aarch64/mte.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ pub unsafe fn __arm_mte_create_random_tag<T>(src: *const T, mask: u64) -> *const
6767
/// SAFETY: See `__arm_mte_create_random_tag`.
6868
#[inline]
6969
#[target_feature(enable = "mte")]
70+
#[rustc_legacy_const_generics(1)]
7071
#[unstable(feature = "stdarch_aarch64_mte", issue = "129010")]
7172
pub unsafe fn __arm_mte_increment_tag<const OFFSET: i64, T>(src: *const T) -> *const T {
7273
addg_(src as *const (), OFFSET) as *const T

‎crates/core_arch/src/loongarch32/mod.rs‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ unsafe extern "unadjusted" {
1616

1717
/// Generates the cache operation instruction
1818
#[inline]
19+
#[rustc_legacy_const_generics(2)]
1920
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
2021
pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) {
2122
static_assert_simm_bits!(IMM12, 12);
@@ -24,6 +25,7 @@ pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) {
2425

2526
/// Reads the CSR
2627
#[inline]
28+
#[rustc_legacy_const_generics(0)]
2729
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
2830
pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
2931
static_assert_uimm_bits!(IMM14, 14);
@@ -32,6 +34,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
3234

3335
/// Writes the CSR
3436
#[inline]
37+
#[rustc_legacy_const_generics(1)]
3538
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
3639
pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
3740
static_assert_uimm_bits!(IMM14, 14);
@@ -40,6 +43,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
4043

4144
/// Exchanges the CSR
4245
#[inline]
46+
#[rustc_legacy_const_generics(2)]
4347
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
4448
pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
4549
static_assert_uimm_bits!(IMM14, 14);

‎crates/core_arch/src/loongarch64/mod.rs‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ pub fn crcc_w_d_w(a: i64, b: i32) -> i32 {
6363

6464
/// Generates the cache operation instruction
6565
#[inline]
66+
#[rustc_legacy_const_generics(2)]
6667
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
6768
pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) {
6869
static_assert_simm_bits!(IMM12, 12);
@@ -71,6 +72,7 @@ pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) {
7172

7273
/// Reads the CSR
7374
#[inline]
75+
#[rustc_legacy_const_generics(0)]
7476
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
7577
pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
7678
static_assert_uimm_bits!(IMM14, 14);
@@ -79,6 +81,7 @@ pub unsafe fn csrrd<const IMM14: i32>() -> i64 {
7981

8082
/// Writes the CSR
8183
#[inline]
84+
#[rustc_legacy_const_generics(1)]
8285
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
8386
pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
8487
static_assert_uimm_bits!(IMM14, 14);
@@ -87,6 +90,7 @@ pub unsafe fn csrwr<const IMM14: i32>(a: i64) -> i64 {
8790

8891
/// Exchanges the CSR
8992
#[inline]
93+
#[rustc_legacy_const_generics(2)]
9094
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
9195
pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {
9296
static_assert_uimm_bits!(IMM14, 14);

‎crates/core_arch/src/loongarch_shared/mod.rs‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
114114

115115
/// Generates the memory barrier instruction
116116
#[inline]
117+
#[rustc_legacy_const_generics(0)]
117118
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
118119
pub fn dbar<const IMM15: i32>() {
119120
static_assert_uimm_bits!(IMM15, 15);
@@ -122,6 +123,7 @@ pub fn dbar<const IMM15: i32>() {
122123

123124
/// Generates the instruction-fetch barrier instruction
124125
#[inline]
126+
#[rustc_legacy_const_generics(0)]
125127
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
126128
pub fn ibar<const IMM15: i32>() {
127129
static_assert_uimm_bits!(IMM15, 15);
@@ -130,6 +132,7 @@ pub fn ibar<const IMM15: i32>() {
130132

131133
/// Moves data from a GPR to the FCSR
132134
#[inline]
135+
#[rustc_legacy_const_generics(1)]
133136
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
134137
pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
135138
static_assert_uimm_bits!(IMM5, 5);
@@ -138,6 +141,7 @@ pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
138141

139142
/// Moves data from a FCSR to the GPR
140143
#[inline]
144+
#[rustc_legacy_const_generics(0)]
141145
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
142146
pub fn movfcsr2gr<const IMM5: i32>() -> i32 {
143147
static_assert_uimm_bits!(IMM5, 5);
@@ -188,6 +192,7 @@ pub unsafe fn iocsrwr_w(a: i32, b: i32) {
188192

189193
/// Generates the breakpoint instruction
190194
#[inline]
195+
#[rustc_legacy_const_generics(0)]
191196
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
192197
pub unsafe fn brk<const IMM15: i32>() {
193198
static_assert_uimm_bits!(IMM15, 15);
@@ -203,6 +208,7 @@ pub fn cpucfg(a: i32) -> i32 {
203208

204209
/// Generates the syscall instruction
205210
#[inline]
211+
#[rustc_legacy_const_generics(0)]
206212
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
207213
pub unsafe fn syscall<const IMM15: i32>() {
208214
static_assert_uimm_bits!(IMM15, 15);

‎crates/core_arch/src/powerpc/altivec.rs‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3244,6 +3244,7 @@ mod sealed {
32443244
/// elements in the vector to determine the element position.
32453245
#[inline]
32463246
#[target_feature(enable = "altivec")]
3247+
#[rustc_legacy_const_generics(2)]
32473248
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
32483249
pub unsafe fn vec_insert<T, const IDX: u32>(a: T, b: <T as sealed::VectorInsert>::Scalar) -> T
32493250
where
@@ -3262,6 +3263,7 @@ where
32623263
/// elements of a.
32633264
#[inline]
32643265
#[target_feature(enable = "altivec")]
3266+
#[rustc_legacy_const_generics(1)]
32653267
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
32663268
pub unsafe fn vec_extract<T, const IDX: u32>(a: T) -> <T as sealed::VectorExtract>::Scalar
32673269
where
@@ -3395,6 +3397,7 @@ where
33953397
/// always to the left. This will generally produce surprising results for little-endian targets.
33963398
#[inline]
33973399
#[target_feature(enable = "altivec")]
3400+
#[rustc_legacy_const_generics(2)]
33983401
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
33993402
pub unsafe fn vec_sld<T, const UIMM4: i32>(a: T, b: T) -> T
34003403
where
@@ -3414,6 +3417,7 @@ where
34143417
/// always to the left. This will generally produce surprising results for little- endian targets.
34153418
#[inline]
34163419
#[target_feature(enable = "altivec")]
3420+
#[rustc_legacy_const_generics(2)]
34173421
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
34183422
pub unsafe fn vec_sldw<T, const UIMM2: i32>(a: T, b: T) -> T
34193423
where
@@ -3933,6 +3937,7 @@ where
39333937
/// Vector Splat
39343938
#[inline]
39353939
#[target_feature(enable = "altivec")]
3940+
#[rustc_legacy_const_generics(1)]
39363941
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
39373942
pub unsafe fn vec_splat<T, const IMM: u32>(a: T) -> T
39383943
where
@@ -4062,6 +4067,7 @@ where
40624067
/// Vector Convert to Floating-Point
40634068
#[inline]
40644069
#[target_feature(enable = "altivec")]
4070+
#[rustc_legacy_const_generics(1)]
40654071
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
40664072
pub unsafe fn vec_ctf<const IMM5: i32, T>(a: T) -> vector_float
40674073
where
@@ -4073,6 +4079,7 @@ where
40734079
/// Vector Convert to Signed Integer
40744080
#[inline]
40754081
#[target_feature(enable = "altivec")]
4082+
#[rustc_legacy_const_generics(1)]
40764083
#[cfg_attr(test, assert_instr(vctsxs, IMM5 = 1))]
40774084
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
40784085
pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
@@ -4084,6 +4091,7 @@ pub unsafe fn vec_cts<const IMM5: i32>(a: vector_float) -> vector_signed_int {
40844091
/// Vector Convert to Unsigned Integer
40854092
#[inline]
40864093
#[target_feature(enable = "altivec")]
4094+
#[rustc_legacy_const_generics(1)]
40874095
#[cfg_attr(test, assert_instr(vctuxs, IMM5 = 1))]
40884096
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
40894097
pub unsafe fn vec_ctu<const IMM5: i32>(a: vector_float) -> vector_unsigned_int {

‎crates/core_arch/src/s390x/vector.rs‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4148,6 +4148,7 @@ pub unsafe fn vec_sqrt<T: sealed::VectorSqrt>(a: T) -> T {
41484148
/// Vector Splat
41494149
#[inline]
41504150
#[target_feature(enable = "vector")]
4151+
#[rustc_legacy_const_generics(1)]
41514152
#[unstable(feature = "stdarch_s390x", issue = "135681")]
41524153
pub unsafe fn vec_splat<T: sealed::VectorSplat, const IMM: u32>(a: T) -> T {
41534154
a.vec_splat::<IMM>()
@@ -4558,6 +4559,7 @@ pub unsafe fn vec_unpackl<T: sealed::VectorUnpackl>(a: T) -> <T as sealed::Vecto
45584559
/// in the corresponding byte element of d are set to ones. Otherwise, if the bit is zero, the corresponding byte element is set to zero.
45594560
#[inline]
45604561
#[target_feature(enable = "vector")]
4562+
#[rustc_legacy_const_generics(0)]
45614563
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45624564
#[cfg_attr(test, assert_instr(vgbm, MASK = 0x00FF))]
45634565
pub unsafe fn vec_genmask<const MASK: u16>() -> vector_unsigned_char {
@@ -4567,6 +4569,7 @@ pub unsafe fn vec_genmask<const MASK: u16>() -> vector_unsigned_char {
45674569
/// Vector Generate Mask (Byte)
45684570
#[inline]
45694571
#[target_feature(enable = "vector")]
4572+
#[rustc_legacy_const_generics(0, 1)]
45704573
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45714574
#[cfg_attr(test, assert_instr(vrepib, L = 3, H = 5))]
45724575
pub unsafe fn vec_genmasks_8<const L: u8, const H: u8>() -> vector_unsigned_char {
@@ -4576,6 +4579,7 @@ pub unsafe fn vec_genmasks_8<const L: u8, const H: u8>() -> vector_unsigned_char
45764579
/// Vector Generate Mask (Halfword)
45774580
#[inline]
45784581
#[target_feature(enable = "vector")]
4582+
#[rustc_legacy_const_generics(0, 1)]
45794583
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45804584
#[cfg_attr(test, assert_instr(vrepih, L = 3, H = 5))]
45814585
pub unsafe fn vec_genmasks_16<const L: u8, const H: u8>() -> vector_unsigned_short {
@@ -4585,6 +4589,7 @@ pub unsafe fn vec_genmasks_16<const L: u8, const H: u8>() -> vector_unsigned_sho
45854589
/// Vector Generate Mask (Word)
45864590
#[inline]
45874591
#[target_feature(enable = "vector")]
4592+
#[rustc_legacy_const_generics(0, 1)]
45884593
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45894594
#[cfg_attr(test, assert_instr(vgmf, L = 3, H = 5))]
45904595
pub unsafe fn vec_genmasks_32<const L: u8, const H: u8>() -> vector_unsigned_int {
@@ -4594,6 +4599,7 @@ pub unsafe fn vec_genmasks_32<const L: u8, const H: u8>() -> vector_unsigned_int
45944599
/// Vector Generate Mask (Doubleword)
45954600
#[inline]
45964601
#[target_feature(enable = "vector")]
4602+
#[rustc_legacy_const_generics(0, 1)]
45974603
#[unstable(feature = "stdarch_s390x", issue = "135681")]
45984604
#[cfg_attr(test, assert_instr(vgmg, L = 3, H = 5))]
45994605
pub unsafe fn vec_genmasks_64<const L: u8, const H: u8>() -> vector_unsigned_long_long {
@@ -4810,6 +4816,7 @@ pub unsafe fn vec_subec_u128(
48104816
/// Vector Splat Signed Byte
48114817
#[inline]
48124818
#[target_feature(enable = "vector")]
4819+
#[rustc_legacy_const_generics(0)]
48134820
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48144821
#[cfg_attr(test, assert_instr(vrepib, IMM = 42))]
48154822
pub unsafe fn vec_splat_s8<const IMM: i8>() -> vector_signed_char {
@@ -4819,6 +4826,7 @@ pub unsafe fn vec_splat_s8<const IMM: i8>() -> vector_signed_char {
48194826
/// Vector Splat Signed Halfword
48204827
#[inline]
48214828
#[target_feature(enable = "vector")]
4829+
#[rustc_legacy_const_generics(0)]
48224830
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48234831
#[cfg_attr(test, assert_instr(vrepih, IMM = 42))]
48244832
pub unsafe fn vec_splat_s16<const IMM: i16>() -> vector_signed_short {
@@ -4828,6 +4836,7 @@ pub unsafe fn vec_splat_s16<const IMM: i16>() -> vector_signed_short {
48284836
/// Vector Splat Signed Word
48294837
#[inline]
48304838
#[target_feature(enable = "vector")]
4839+
#[rustc_legacy_const_generics(0)]
48314840
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48324841
#[cfg_attr(test, assert_instr(vrepif, IMM = 42))]
48334842
pub unsafe fn vec_splat_s32<const IMM: i16>() -> vector_signed_int {
@@ -4837,6 +4846,7 @@ pub unsafe fn vec_splat_s32<const IMM: i16>() -> vector_signed_int {
48374846
/// Vector Splat Signed Doubleword
48384847
#[inline]
48394848
#[target_feature(enable = "vector")]
4849+
#[rustc_legacy_const_generics(0)]
48404850
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48414851
#[cfg_attr(test, assert_instr(vrepig, IMM = 42))]
48424852
pub unsafe fn vec_splat_s64<const IMM: i16>() -> vector_signed_long_long {
@@ -4846,6 +4856,7 @@ pub unsafe fn vec_splat_s64<const IMM: i16>() -> vector_signed_long_long {
48464856
/// Vector Splat Unsigned Byte
48474857
#[inline]
48484858
#[target_feature(enable = "vector")]
4859+
#[rustc_legacy_const_generics(0)]
48494860
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48504861
#[cfg_attr(test, assert_instr(vrepib, IMM = 42))]
48514862
pub unsafe fn vec_splat_u8<const IMM: u8>() -> vector_unsigned_char {
@@ -4855,6 +4866,7 @@ pub unsafe fn vec_splat_u8<const IMM: u8>() -> vector_unsigned_char {
48554866
/// Vector Splat Unsigned Halfword
48564867
#[inline]
48574868
#[target_feature(enable = "vector")]
4869+
#[rustc_legacy_const_generics(0)]
48584870
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48594871
#[cfg_attr(test, assert_instr(vrepih, IMM = 42))]
48604872
pub unsafe fn vec_splat_u16<const IMM: i16>() -> vector_unsigned_short {
@@ -4864,6 +4876,7 @@ pub unsafe fn vec_splat_u16<const IMM: i16>() -> vector_unsigned_short {
48644876
/// Vector Splat Unsigned Word
48654877
#[inline]
48664878
#[target_feature(enable = "vector")]
4879+
#[rustc_legacy_const_generics(0)]
48674880
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48684881
#[cfg_attr(test, assert_instr(vrepif, IMM = 42))]
48694882
pub unsafe fn vec_splat_u32<const IMM: i16>() -> vector_unsigned_int {
@@ -4873,6 +4886,7 @@ pub unsafe fn vec_splat_u32<const IMM: i16>() -> vector_unsigned_int {
48734886
/// Vector Splat Unsigned Doubleword
48744887
#[inline]
48754888
#[target_feature(enable = "vector")]
4889+
#[rustc_legacy_const_generics(0)]
48764890
#[unstable(feature = "stdarch_s390x", issue = "135681")]
48774891
#[cfg_attr(test, assert_instr(vrepig, IMM = 42))]
48784892
pub unsafe fn vec_splat_u64<const IMM: i16>() -> vector_unsigned_long_long {
@@ -4944,6 +4958,7 @@ pub unsafe fn vec_load_pair<T: sealed::VectorLoadPair>(a: T::ElementType, b: T::
49444958
/// Vector Load to Block Boundary
49454959
#[inline]
49464960
#[target_feature(enable = "vector")]
4961+
#[rustc_legacy_const_generics(1)]
49474962
#[unstable(feature = "stdarch_s390x", issue = "135681")]
49484963
pub unsafe fn vec_load_bndry<T: sealed::VectorLoad, const BLOCK_BOUNDARY: u16>(
49494964
ptr: *const T::ElementType,
@@ -5141,6 +5156,7 @@ pub unsafe fn vec_bperm_u128(
51415156
/// Vector Gather Element
51425157
#[inline]
51435158
#[target_feature(enable = "vector")]
5159+
#[rustc_legacy_const_generics(3)]
51445160
#[unstable(feature = "stdarch_s390x", issue = "135681")]
51455161
pub unsafe fn vec_gather_element<T: sealed::VectorGatherElement, const D: u32>(
51465162
a: T,
@@ -5205,6 +5221,7 @@ pub const __VEC_CLASS_FP_NOT_NORMAL: u32 =
52055221
/// You can use the `__VEC_CLASS_FP_*` constants as the argument for this operand
52065222
#[inline]
52075223
#[target_feature(enable = "vector")]
5224+
#[rustc_legacy_const_generics(1)]
52085225
#[unstable(feature = "stdarch_s390x", issue = "135681")]
52095226
pub unsafe fn vec_fp_test_data_class<T: sealed::VectorFpTestDataClass, const CLASS: u32>(
52105227
a: T,
@@ -5366,6 +5383,7 @@ pub unsafe fn vec_cp_until_zero_cc<T: sealed::VectorCopyUntilZeroCC>(a: T) -> (T
53665383
/// Vector Multiply Sum Logical
53675384
#[inline]
53685385
#[target_feature(enable = "vector-enhancements-1")]
5386+
#[rustc_legacy_const_generics(3)]
53695387
#[unstable(feature = "stdarch_s390x", issue = "135681")]
53705388
#[cfg_attr(
53715389
all(test, target_feature = "vector-enhancements-1"),
@@ -5387,6 +5405,7 @@ pub unsafe fn vec_msum_u128<const D: u32>(
53875405
/// Vector Shift Left Double by Byte
53885406
#[inline]
53895407
#[target_feature(enable = "vector")]
5408+
#[rustc_legacy_const_generics(2)]
53905409
#[unstable(feature = "stdarch_s390x", issue = "135681")]
53915410
pub unsafe fn vec_sld<T: sealed::VectorSld, const C: u32>(a: T, b: T) -> T {
53925411
static_assert_uimm_bits!(C, 4);
@@ -5396,6 +5415,7 @@ pub unsafe fn vec_sld<T: sealed::VectorSld, const C: u32>(a: T, b: T) -> T {
53965415
/// Vector Shift Left Double by Word
53975416
#[inline]
53985417
#[target_feature(enable = "vector")]
5418+
#[rustc_legacy_const_generics(2)]
53995419
#[unstable(feature = "stdarch_s390x", issue = "135681")]
54005420
pub unsafe fn vec_sldw<T: sealed::VectorSld, const C: u32>(a: T, b: T) -> T {
54015421
static_assert_uimm_bits!(C, 2);
@@ -5405,6 +5425,7 @@ pub unsafe fn vec_sldw<T: sealed::VectorSld, const C: u32>(a: T, b: T) -> T {
54055425
/// Vector Shift Left Double by Bit
54065426
#[inline]
54075427
#[target_feature(enable = "vector-enhancements-2")]
5428+
#[rustc_legacy_const_generics(2)]
54085429
#[unstable(feature = "stdarch_s390x", issue = "135681")]
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pub unsafe fn vec_sldb<T: sealed::VectorSld, const C: u32>(a: T, b: T) -> T {
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static_assert_uimm_bits!(C, 3);
@@ -5414,6 +5435,7 @@ pub unsafe fn vec_sldb<T: sealed::VectorSld, const C: u32>(a: T, b: T) -> T {
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/// Vector Shift Right Double by Bit
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#[inline]
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#[target_feature(enable = "vector-enhancements-2")]
5438+
#[rustc_legacy_const_generics(2)]
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#[unstable(feature = "stdarch_s390x", issue = "135681")]
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pub unsafe fn vec_srdb<T: sealed::VectorSrdb, const C: u32>(a: T, b: T) -> T {
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static_assert_uimm_bits!(C, 3);

‎crates/core_arch/src/wasm32/mod.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,7 @@ unsafe extern "C-unwind" {
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// reenable this attribute.
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// #[cfg_attr(test, assert_instr(throw, TAG = 0, ptr = core::ptr::null_mut()))]
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#[inline]
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#[rustc_legacy_const_generics(1)]
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#[unstable(feature = "wasm_exception_handling_intrinsics", issue = "122465")]
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// FIXME: Since this instruction unwinds, `core` built with `-C panic=unwind`
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// cannot be linked with `-C panic=abort` programs. But that's not

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