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rustc_abi::Abi to IrForm in cg_llvm
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5 files changed

+72
-69
lines changed

5 files changed

+72
-69
lines changed

‎compiler/rustc_codegen_llvm/src/abi.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ impl<'ll, 'tcx> FnAbiLlvmExt<'ll, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
458458
match &self.ret.mode {
459459
PassMode::Direct(attrs) => {
460460
attrs.apply_attrs_to_llfn(llvm::AttributePlace::ReturnValue, cx, llfn);
461-
if let abi::Abi::Scalar(scalar) = self.ret.layout.abi {
461+
if let abi::IrForm::Scalar(scalar) = self.ret.layout.ir_form {
462462
apply_range_attr(llvm::AttributePlace::ReturnValue, scalar);
463463
}
464464
}
@@ -495,7 +495,7 @@ impl<'ll, 'tcx> FnAbiLlvmExt<'ll, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
495495
}
496496
PassMode::Direct(attrs) => {
497497
let i = apply(attrs);
498-
if let abi::Abi::Scalar(scalar) = arg.layout.abi {
498+
if let abi::IrForm::Scalar(scalar) = arg.layout.ir_form {
499499
apply_range_attr(llvm::AttributePlace::Argument(i), scalar);
500500
}
501501
}
@@ -510,7 +510,7 @@ impl<'ll, 'tcx> FnAbiLlvmExt<'ll, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
510510
PassMode::Pair(a, b) => {
511511
let i = apply(a);
512512
let ii = apply(b);
513-
if let abi::Abi::ScalarPair(scalar_a, scalar_b) = arg.layout.abi {
513+
if let abi::IrForm::ScalarPair(scalar_a, scalar_b) = arg.layout.ir_form {
514514
apply_range_attr(llvm::AttributePlace::Argument(i), scalar_a);
515515
apply_range_attr(llvm::AttributePlace::Argument(ii), scalar_b);
516516
}
@@ -570,7 +570,7 @@ impl<'ll, 'tcx> FnAbiLlvmExt<'ll, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
570570
}
571571
if bx.cx.sess().opts.optimize != config::OptLevel::No
572572
&& llvm_util::get_version() < (19, 0, 0)
573-
&& let abi::Abi::Scalar(scalar) = self.ret.layout.abi
573+
&& let abi::IrForm::Scalar(scalar) = self.ret.layout.ir_form
574574
&& matches!(scalar.primitive(), Int(..))
575575
// If the value is a boolean, the range is 0..2 and that ultimately
576576
// become 0..0 when the type becomes i1, which would be rejected

‎compiler/rustc_codegen_llvm/src/asm.rs‎

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -880,16 +880,16 @@ fn llvm_fixup_input<'ll, 'tcx>(
880880
) -> &'ll Value {
881881
use InlineAsmRegClass::*;
882882
let dl = &bx.tcx.data_layout;
883-
match (reg, layout.abi) {
884-
(AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
883+
match (reg, layout.ir_form) {
884+
(AArch64(AArch64InlineAsmRegClass::vreg), IrForm::Scalar(s)) => {
885885
if let Primitive::Int(Integer::I8, _) = s.primitive() {
886886
let vec_ty = bx.cx.type_vector(bx.cx.type_i8(), 8);
887887
bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
888888
} else {
889889
value
890890
}
891891
}
892-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s))
892+
(AArch64(AArch64InlineAsmRegClass::vreg_low16), IrForm::Scalar(s))
893893
if s.primitive() != Primitive::Float(Float::F128) =>
894894
{
895895
let elem_ty = llvm_asm_scalar_type(bx.cx, s);
@@ -902,30 +902,30 @@ fn llvm_fixup_input<'ll, 'tcx>(
902902
}
903903
bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
904904
}
905-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Vector { element, count })
905+
(AArch64(AArch64InlineAsmRegClass::vreg_low16), IrForm::Vector { element, count })
906906
if layout.size.bytes() == 8 =>
907907
{
908908
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
909909
let vec_ty = bx.cx.type_vector(elem_ty, count);
910910
let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
911911
bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
912912
}
913-
(X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
913+
(X86(X86InlineAsmRegClass::reg_abcd), IrForm::Scalar(s))
914914
if s.primitive() == Primitive::Float(Float::F64) =>
915915
{
916916
bx.bitcast(value, bx.cx.type_i64())
917917
}
918918
(
919919
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
920-
Abi::Vector { .. },
920+
IrForm::Vector { .. },
921921
) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
922922
(
923923
X86(
924924
X86InlineAsmRegClass::xmm_reg
925925
| X86InlineAsmRegClass::ymm_reg
926926
| X86InlineAsmRegClass::zmm_reg,
927927
),
928-
Abi::Scalar(s),
928+
IrForm::Scalar(s),
929929
) if bx.sess().asm_arch == Some(InlineAsmArch::X86)
930930
&& s.primitive() == Primitive::Float(Float::F128) =>
931931
{
@@ -937,7 +937,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
937937
| X86InlineAsmRegClass::ymm_reg
938938
| X86InlineAsmRegClass::zmm_reg,
939939
),
940-
Abi::Scalar(s),
940+
IrForm::Scalar(s),
941941
) if s.primitive() == Primitive::Float(Float::F16) => {
942942
let value = bx.insert_element(
943943
bx.const_undef(bx.type_vector(bx.type_f16(), 8)),
@@ -952,11 +952,11 @@ fn llvm_fixup_input<'ll, 'tcx>(
952952
| X86InlineAsmRegClass::ymm_reg
953953
| X86InlineAsmRegClass::zmm_reg,
954954
),
955-
Abi::Vector { element, count: count @ (8 | 16) },
955+
IrForm::Vector { element, count: count @ (8 | 16) },
956956
) if element.primitive() == Primitive::Float(Float::F16) => {
957957
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
958958
}
959-
(Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16), Abi::Scalar(s)) => {
959+
(Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16), IrForm::Scalar(s)) => {
960960
if let Primitive::Int(Integer::I32, _) = s.primitive() {
961961
bx.bitcast(value, bx.cx.type_f32())
962962
} else {
@@ -969,7 +969,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
969969
| ArmInlineAsmRegClass::dreg_low8
970970
| ArmInlineAsmRegClass::dreg_low16,
971971
),
972-
Abi::Scalar(s),
972+
IrForm::Scalar(s),
973973
) => {
974974
if let Primitive::Int(Integer::I64, _) = s.primitive() {
975975
bx.bitcast(value, bx.cx.type_f64())
@@ -986,11 +986,11 @@ fn llvm_fixup_input<'ll, 'tcx>(
986986
| ArmInlineAsmRegClass::qreg_low4
987987
| ArmInlineAsmRegClass::qreg_low8,
988988
),
989-
Abi::Vector { element, count: count @ (4 | 8) },
989+
IrForm::Vector { element, count: count @ (4 | 8) },
990990
) if element.primitive() == Primitive::Float(Float::F16) => {
991991
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
992992
}
993-
(Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
993+
(Mips(MipsInlineAsmRegClass::reg), IrForm::Scalar(s)) => {
994994
match s.primitive() {
995995
// MIPS only supports register-length arithmetics.
996996
Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
@@ -999,7 +999,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
999999
_ => value,
10001000
}
10011001
}
1002-
(RiscV(RiscVInlineAsmRegClass::freg), Abi::Scalar(s))
1002+
(RiscV(RiscVInlineAsmRegClass::freg), IrForm::Scalar(s))
10031003
if s.primitive() == Primitive::Float(Float::F16)
10041004
&& !any_target_feature_enabled(bx, instance, &[sym::zfhmin, sym::zfh]) =>
10051005
{
@@ -1022,15 +1022,15 @@ fn llvm_fixup_output<'ll, 'tcx>(
10221022
instance: Instance<'_>,
10231023
) -> &'ll Value {
10241024
use InlineAsmRegClass::*;
1025-
match (reg, layout.abi) {
1026-
(AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
1025+
match (reg, layout.ir_form) {
1026+
(AArch64(AArch64InlineAsmRegClass::vreg), IrForm::Scalar(s)) => {
10271027
if let Primitive::Int(Integer::I8, _) = s.primitive() {
10281028
bx.extract_element(value, bx.const_i32(0))
10291029
} else {
10301030
value
10311031
}
10321032
}
1033-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s))
1033+
(AArch64(AArch64InlineAsmRegClass::vreg_low16), IrForm::Scalar(s))
10341034
if s.primitive() != Primitive::Float(Float::F128) =>
10351035
{
10361036
value = bx.extract_element(value, bx.const_i32(0));
@@ -1039,30 +1039,30 @@ fn llvm_fixup_output<'ll, 'tcx>(
10391039
}
10401040
value
10411041
}
1042-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Vector { element, count })
1042+
(AArch64(AArch64InlineAsmRegClass::vreg_low16), IrForm::Vector { element, count })
10431043
if layout.size.bytes() == 8 =>
10441044
{
10451045
let elem_ty = llvm_asm_scalar_type(bx.cx, element);
10461046
let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
10471047
let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
10481048
bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
10491049
}
1050-
(X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
1050+
(X86(X86InlineAsmRegClass::reg_abcd), IrForm::Scalar(s))
10511051
if s.primitive() == Primitive::Float(Float::F64) =>
10521052
{
10531053
bx.bitcast(value, bx.cx.type_f64())
10541054
}
10551055
(
10561056
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
1057-
Abi::Vector { .. },
1057+
IrForm::Vector { .. },
10581058
) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
10591059
(
10601060
X86(
10611061
X86InlineAsmRegClass::xmm_reg
10621062
| X86InlineAsmRegClass::ymm_reg
10631063
| X86InlineAsmRegClass::zmm_reg,
10641064
),
1065-
Abi::Scalar(s),
1065+
IrForm::Scalar(s),
10661066
) if bx.sess().asm_arch == Some(InlineAsmArch::X86)
10671067
&& s.primitive() == Primitive::Float(Float::F128) =>
10681068
{
@@ -1074,7 +1074,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
10741074
| X86InlineAsmRegClass::ymm_reg
10751075
| X86InlineAsmRegClass::zmm_reg,
10761076
),
1077-
Abi::Scalar(s),
1077+
IrForm::Scalar(s),
10781078
) if s.primitive() == Primitive::Float(Float::F16) => {
10791079
let value = bx.bitcast(value, bx.type_vector(bx.type_f16(), 8));
10801080
bx.extract_element(value, bx.const_usize(0))
@@ -1085,11 +1085,11 @@ fn llvm_fixup_output<'ll, 'tcx>(
10851085
| X86InlineAsmRegClass::ymm_reg
10861086
| X86InlineAsmRegClass::zmm_reg,
10871087
),
1088-
Abi::Vector { element, count: count @ (8 | 16) },
1088+
IrForm::Vector { element, count: count @ (8 | 16) },
10891089
) if element.primitive() == Primitive::Float(Float::F16) => {
10901090
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
10911091
}
1092-
(Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16), Abi::Scalar(s)) => {
1092+
(Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16), IrForm::Scalar(s)) => {
10931093
if let Primitive::Int(Integer::I32, _) = s.primitive() {
10941094
bx.bitcast(value, bx.cx.type_i32())
10951095
} else {
@@ -1102,7 +1102,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
11021102
| ArmInlineAsmRegClass::dreg_low8
11031103
| ArmInlineAsmRegClass::dreg_low16,
11041104
),
1105-
Abi::Scalar(s),
1105+
IrForm::Scalar(s),
11061106
) => {
11071107
if let Primitive::Int(Integer::I64, _) = s.primitive() {
11081108
bx.bitcast(value, bx.cx.type_i64())
@@ -1119,11 +1119,11 @@ fn llvm_fixup_output<'ll, 'tcx>(
11191119
| ArmInlineAsmRegClass::qreg_low4
11201120
| ArmInlineAsmRegClass::qreg_low8,
11211121
),
1122-
Abi::Vector { element, count: count @ (4 | 8) },
1122+
IrForm::Vector { element, count: count @ (4 | 8) },
11231123
) if element.primitive() == Primitive::Float(Float::F16) => {
11241124
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
11251125
}
1126-
(Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
1126+
(Mips(MipsInlineAsmRegClass::reg), IrForm::Scalar(s)) => {
11271127
match s.primitive() {
11281128
// MIPS only supports register-length arithmetics.
11291129
Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
@@ -1133,7 +1133,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
11331133
_ => value,
11341134
}
11351135
}
1136-
(RiscV(RiscVInlineAsmRegClass::freg), Abi::Scalar(s))
1136+
(RiscV(RiscVInlineAsmRegClass::freg), IrForm::Scalar(s))
11371137
if s.primitive() == Primitive::Float(Float::F16)
11381138
&& !any_target_feature_enabled(bx, instance, &[sym::zfhmin, sym::zfh]) =>
11391139
{
@@ -1153,43 +1153,43 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
11531153
instance: Instance<'_>,
11541154
) -> &'ll Type {
11551155
use InlineAsmRegClass::*;
1156-
match (reg, layout.abi) {
1157-
(AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
1156+
match (reg, layout.ir_form) {
1157+
(AArch64(AArch64InlineAsmRegClass::vreg), IrForm::Scalar(s)) => {
11581158
if let Primitive::Int(Integer::I8, _) = s.primitive() {
11591159
cx.type_vector(cx.type_i8(), 8)
11601160
} else {
11611161
layout.llvm_type(cx)
11621162
}
11631163
}
1164-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s))
1164+
(AArch64(AArch64InlineAsmRegClass::vreg_low16), IrForm::Scalar(s))
11651165
if s.primitive() != Primitive::Float(Float::F128) =>
11661166
{
11671167
let elem_ty = llvm_asm_scalar_type(cx, s);
11681168
let count = 16 / layout.size.bytes();
11691169
cx.type_vector(elem_ty, count)
11701170
}
1171-
(AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Vector { element, count })
1171+
(AArch64(AArch64InlineAsmRegClass::vreg_low16), IrForm::Vector { element, count })
11721172
if layout.size.bytes() == 8 =>
11731173
{
11741174
let elem_ty = llvm_asm_scalar_type(cx, element);
11751175
cx.type_vector(elem_ty, count * 2)
11761176
}
1177-
(X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
1177+
(X86(X86InlineAsmRegClass::reg_abcd), IrForm::Scalar(s))
11781178
if s.primitive() == Primitive::Float(Float::F64) =>
11791179
{
11801180
cx.type_i64()
11811181
}
11821182
(
11831183
X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
1184-
Abi::Vector { .. },
1184+
IrForm::Vector { .. },
11851185
) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
11861186
(
11871187
X86(
11881188
X86InlineAsmRegClass::xmm_reg
11891189
| X86InlineAsmRegClass::ymm_reg
11901190
| X86InlineAsmRegClass::zmm_reg,
11911191
),
1192-
Abi::Scalar(s),
1192+
IrForm::Scalar(s),
11931193
) if cx.sess().asm_arch == Some(InlineAsmArch::X86)
11941194
&& s.primitive() == Primitive::Float(Float::F128) =>
11951195
{
@@ -1201,19 +1201,19 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12011201
| X86InlineAsmRegClass::ymm_reg
12021202
| X86InlineAsmRegClass::zmm_reg,
12031203
),
1204-
Abi::Scalar(s),
1204+
IrForm::Scalar(s),
12051205
) if s.primitive() == Primitive::Float(Float::F16) => cx.type_vector(cx.type_i16(), 8),
12061206
(
12071207
X86(
12081208
X86InlineAsmRegClass::xmm_reg
12091209
| X86InlineAsmRegClass::ymm_reg
12101210
| X86InlineAsmRegClass::zmm_reg,
12111211
),
1212-
Abi::Vector { element, count: count @ (8 | 16) },
1212+
IrForm::Vector { element, count: count @ (8 | 16) },
12131213
) if element.primitive() == Primitive::Float(Float::F16) => {
12141214
cx.type_vector(cx.type_i16(), count)
12151215
}
1216-
(Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16), Abi::Scalar(s)) => {
1216+
(Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16), IrForm::Scalar(s)) => {
12171217
if let Primitive::Int(Integer::I32, _) = s.primitive() {
12181218
cx.type_f32()
12191219
} else {
@@ -1226,7 +1226,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12261226
| ArmInlineAsmRegClass::dreg_low8
12271227
| ArmInlineAsmRegClass::dreg_low16,
12281228
),
1229-
Abi::Scalar(s),
1229+
IrForm::Scalar(s),
12301230
) => {
12311231
if let Primitive::Int(Integer::I64, _) = s.primitive() {
12321232
cx.type_f64()
@@ -1243,11 +1243,11 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12431243
| ArmInlineAsmRegClass::qreg_low4
12441244
| ArmInlineAsmRegClass::qreg_low8,
12451245
),
1246-
Abi::Vector { element, count: count @ (4 | 8) },
1246+
IrForm::Vector { element, count: count @ (4 | 8) },
12471247
) if element.primitive() == Primitive::Float(Float::F16) => {
12481248
cx.type_vector(cx.type_i16(), count)
12491249
}
1250-
(Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
1250+
(Mips(MipsInlineAsmRegClass::reg), IrForm::Scalar(s)) => {
12511251
match s.primitive() {
12521252
// MIPS only supports register-length arithmetics.
12531253
Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
@@ -1256,7 +1256,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
12561256
_ => layout.llvm_type(cx),
12571257
}
12581258
}
1259-
(RiscV(RiscVInlineAsmRegClass::freg), Abi::Scalar(s))
1259+
(RiscV(RiscVInlineAsmRegClass::freg), IrForm::Scalar(s))
12601260
if s.primitive() == Primitive::Float(Float::F16)
12611261
&& !any_target_feature_enabled(cx, instance, &[sym::zfhmin, sym::zfh]) =>
12621262
{

‎compiler/rustc_codegen_llvm/src/builder.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -545,13 +545,13 @@ impl<'a, 'll, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'll, 'tcx> {
545545
}
546546
let llval = const_llval.unwrap_or_else(|| {
547547
let load = self.load(llty, place.val.llval, place.val.align);
548-
if let abi::Abi::Scalar(scalar) = place.layout.abi {
548+
if let abi::IrForm::Scalar(scalar) = place.layout.ir_form {
549549
scalar_load_metadata(self, load, scalar, place.layout, Size::ZERO);
550550
}
551551
load
552552
});
553553
OperandValue::Immediate(self.to_immediate(llval, place.layout))
554-
} else if let abi::Abi::ScalarPair(a, b) = place.layout.abi {
554+
} else if let abi::IrForm::ScalarPair(a, b) = place.layout.ir_form {
555555
let b_offset = a.size(self).align_to(b.align(self).abi);
556556

557557
let mut load = |i, scalar: abi::Scalar, layout, align, offset| {

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