@@ -962,6 +962,37 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
962962 }
963963 }
964964
965+ sym:: simd_masked_store => {
966+ intrinsic_args ! ( fx, args => ( mask, ptr, val) ; intrinsic) ;
967+
968+ let ( val_lane_count, val_lane_ty) = val. layout ( ) . ty . simd_size_and_type ( fx. tcx ) ;
969+ let ( mask_lane_count, _mask_lane_ty) = mask. layout ( ) . ty . simd_size_and_type ( fx. tcx ) ;
970+ assert_eq ! ( val_lane_count, mask_lane_count) ;
971+ let lane_clif_ty = fx. clif_type ( val_lane_ty) . unwrap ( ) ;
972+ let ptr_val = ptr. load_scalar ( fx) ;
973+
974+ for lane_idx in 0 ..val_lane_count {
975+ let val_lane = val. value_lane ( fx, lane_idx) . load_scalar ( fx) ;
976+ let mask_lane = mask. value_lane ( fx, lane_idx) . load_scalar ( fx) ;
977+
978+ let if_enabled = fx. bcx . create_block ( ) ;
979+ let next = fx. bcx . create_block ( ) ;
980+
981+ fx. bcx . ins ( ) . brif ( mask_lane, if_enabled, & [ ] , next, & [ ] ) ;
982+ fx. bcx . seal_block ( if_enabled) ;
983+
984+ fx. bcx . switch_to_block ( if_enabled) ;
985+ let offset = lane_idx as i32 * lane_clif_ty. bytes ( ) as i32 ;
986+ fx. bcx . ins ( ) . store ( MemFlags :: trusted ( ) , val_lane, ptr_val, Offset32 :: new ( offset) ) ;
987+ fx. bcx . ins ( ) . jump ( next, & [ ] ) ;
988+
989+ fx. bcx . seal_block ( next) ;
990+ fx. bcx . switch_to_block ( next) ;
991+
992+ fx. bcx . ins ( ) . nop ( ) ;
993+ }
994+ }
995+
965996 sym:: simd_gather => {
966997 intrinsic_args ! ( fx, args => ( val, ptr, mask) ; intrinsic) ;
967998
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