@@ -910,6 +910,90 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
910910 ) ;
911911 }
912912
913+ "llvm.x86.sha256rnds2" => {
914+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sha256rnds2_epu32&ig_expand=5977
915+ intrinsic_args ! ( fx, args => ( a, b, k) ; intrinsic) ;
916+
917+ let a = a. load_scalar ( fx) ;
918+ let b = b. load_scalar ( fx) ;
919+ let k = k. load_scalar ( fx) ;
920+
921+ codegen_inline_asm_inner (
922+ fx,
923+ & [ InlineAsmTemplatePiece :: String ( "sha256rnds2 xmm1, xmm2" . to_string ( ) ) ] ,
924+ & [
925+ CInlineAsmOperand :: InOut {
926+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm1) ) ,
927+ _late : true ,
928+ in_value : a,
929+ out_place : Some ( ret) ,
930+ } ,
931+ CInlineAsmOperand :: In {
932+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm2) ) ,
933+ value : b,
934+ } ,
935+ // Implicit argument to the sha256rnds2 instruction
936+ CInlineAsmOperand :: In {
937+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm0) ) ,
938+ value : k,
939+ } ,
940+ ] ,
941+ InlineAsmOptions :: NOSTACK | InlineAsmOptions :: PURE | InlineAsmOptions :: NOMEM ,
942+ ) ;
943+ }
944+
945+ "llvm.x86.sha256msg1" => {
946+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sha256msg1_epu32&ig_expand=5975
947+ intrinsic_args ! ( fx, args => ( a, b) ; intrinsic) ;
948+
949+ let a = a. load_scalar ( fx) ;
950+ let b = b. load_scalar ( fx) ;
951+
952+ codegen_inline_asm_inner (
953+ fx,
954+ & [ InlineAsmTemplatePiece :: String ( "sha256msg1 xmm1, xmm2" . to_string ( ) ) ] ,
955+ & [
956+ CInlineAsmOperand :: InOut {
957+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm1) ) ,
958+ _late : true ,
959+ in_value : a,
960+ out_place : Some ( ret) ,
961+ } ,
962+ CInlineAsmOperand :: In {
963+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm2) ) ,
964+ value : b,
965+ } ,
966+ ] ,
967+ InlineAsmOptions :: NOSTACK | InlineAsmOptions :: PURE | InlineAsmOptions :: NOMEM ,
968+ ) ;
969+ }
970+
971+ "llvm.x86.sha256msg2" => {
972+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sha256msg2_epu32&ig_expand=5976
973+ intrinsic_args ! ( fx, args => ( a, b) ; intrinsic) ;
974+
975+ let a = a. load_scalar ( fx) ;
976+ let b = b. load_scalar ( fx) ;
977+
978+ codegen_inline_asm_inner (
979+ fx,
980+ & [ InlineAsmTemplatePiece :: String ( "sha256msg2 xmm1, xmm2" . to_string ( ) ) ] ,
981+ & [
982+ CInlineAsmOperand :: InOut {
983+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm1) ) ,
984+ _late : true ,
985+ in_value : a,
986+ out_place : Some ( ret) ,
987+ } ,
988+ CInlineAsmOperand :: In {
989+ reg : InlineAsmRegOrRegClass :: Reg ( InlineAsmReg :: X86 ( X86InlineAsmReg :: xmm2) ) ,
990+ value : b,
991+ } ,
992+ ] ,
993+ InlineAsmOptions :: NOSTACK | InlineAsmOptions :: PURE | InlineAsmOptions :: NOMEM ,
994+ ) ;
995+ }
996+
913997 "llvm.x86.avx.ptestz.256" => {
914998 // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testz_si256&ig_expand=6945
915999 intrinsic_args ! ( fx, args => ( a, b) ; intrinsic) ;
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