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aarch64: check for trn1 and trn2 
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2 files changed

+89
-19
lines changed

2 files changed

+89
-19
lines changed

‎library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs‎

Lines changed: 85 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -72994,7 +72994,11 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
7299472994
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7299572995
#[cfg_attr(
7299672996
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72997-
assert_instr(trn)
72997+
assert_instr(trn1)
72998+
)]
72999+
#[cfg_attr(
73000+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73001+
assert_instr(trn2)
7299873002
)]
7299973003
#[target_feature(enable = "neon,fp16")]
7300073004
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -73012,7 +73016,11 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
7301273016
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7301373017
#[cfg_attr(
7301473018
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73015-
assert_instr(trn)
73019+
assert_instr(trn1)
73020+
)]
73021+
#[cfg_attr(
73022+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73023+
assert_instr(trn2)
7301673024
)]
7301773025
#[target_feature(enable = "neon,fp16")]
7301873026
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -73118,7 +73126,11 @@ pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
7311873126
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7311973127
#[cfg_attr(
7312073128
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73121-
assert_instr(trn)
73129+
assert_instr(trn1)
73130+
)]
73131+
#[cfg_attr(
73132+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73133+
assert_instr(trn2)
7312273134
)]
7312373135
#[cfg_attr(
7312473136
not(target_arch = "arm"),
@@ -73143,7 +73155,11 @@ pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
7314373155
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7314473156
#[cfg_attr(
7314573157
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73146-
assert_instr(trn)
73158+
assert_instr(trn1)
73159+
)]
73160+
#[cfg_attr(
73161+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73162+
assert_instr(trn2)
7314773163
)]
7314873164
#[cfg_attr(
7314973165
not(target_arch = "arm"),
@@ -73168,7 +73184,11 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
7316873184
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7316973185
#[cfg_attr(
7317073186
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73171-
assert_instr(trn)
73187+
assert_instr(trn1)
73188+
)]
73189+
#[cfg_attr(
73190+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73191+
assert_instr(trn2)
7317273192
)]
7317373193
#[cfg_attr(
7317473194
not(target_arch = "arm"),
@@ -73201,7 +73221,11 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
7320173221
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7320273222
#[cfg_attr(
7320373223
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73204-
assert_instr(trn)
73224+
assert_instr(trn1)
73225+
)]
73226+
#[cfg_attr(
73227+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73228+
assert_instr(trn2)
7320573229
)]
7320673230
#[cfg_attr(
7320773231
not(target_arch = "arm"),
@@ -73226,7 +73250,11 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
7322673250
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7322773251
#[cfg_attr(
7322873252
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73229-
assert_instr(trn)
73253+
assert_instr(trn1)
73254+
)]
73255+
#[cfg_attr(
73256+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73257+
assert_instr(trn2)
7323073258
)]
7323173259
#[cfg_attr(
7323273260
not(target_arch = "arm"),
@@ -73251,7 +73279,11 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
7325173279
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7325273280
#[cfg_attr(
7325373281
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73254-
assert_instr(trn)
73282+
assert_instr(trn1)
73283+
)]
73284+
#[cfg_attr(
73285+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73286+
assert_instr(trn2)
7325573287
)]
7325673288
#[cfg_attr(
7325773289
not(target_arch = "arm"),
@@ -73276,7 +73308,11 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
7327673308
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7327773309
#[cfg_attr(
7327873310
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73279-
assert_instr(trn)
73311+
assert_instr(trn1)
73312+
)]
73313+
#[cfg_attr(
73314+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73315+
assert_instr(trn2)
7328073316
)]
7328173317
#[cfg_attr(
7328273318
not(target_arch = "arm"),
@@ -73301,7 +73337,11 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
7330173337
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7330273338
#[cfg_attr(
7330373339
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73304-
assert_instr(trn)
73340+
assert_instr(trn1)
73341+
)]
73342+
#[cfg_attr(
73343+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73344+
assert_instr(trn2)
7330573345
)]
7330673346
#[cfg_attr(
7330773347
not(target_arch = "arm"),
@@ -73334,7 +73374,11 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
7333473374
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7333573375
#[cfg_attr(
7333673376
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73337-
assert_instr(trn)
73377+
assert_instr(trn1)
73378+
)]
73379+
#[cfg_attr(
73380+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73381+
assert_instr(trn2)
7333873382
)]
7333973383
#[cfg_attr(
7334073384
not(target_arch = "arm"),
@@ -73359,7 +73403,11 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
7335973403
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7336073404
#[cfg_attr(
7336173405
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73362-
assert_instr(trn)
73406+
assert_instr(trn1)
73407+
)]
73408+
#[cfg_attr(
73409+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73410+
assert_instr(trn2)
7336373411
)]
7336473412
#[cfg_attr(
7336573413
not(target_arch = "arm"),
@@ -73384,7 +73432,11 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
7338473432
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7338573433
#[cfg_attr(
7338673434
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73387-
assert_instr(trn)
73435+
assert_instr(trn1)
73436+
)]
73437+
#[cfg_attr(
73438+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73439+
assert_instr(trn2)
7338873440
)]
7338973441
#[cfg_attr(
7339073442
not(target_arch = "arm"),
@@ -73409,7 +73461,11 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
7340973461
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7341073462
#[cfg_attr(
7341173463
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73412-
assert_instr(trn)
73464+
assert_instr(trn1)
73465+
)]
73466+
#[cfg_attr(
73467+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73468+
assert_instr(trn2)
7341373469
)]
7341473470
#[cfg_attr(
7341573471
not(target_arch = "arm"),
@@ -73434,7 +73490,11 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
7343473490
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7343573491
#[cfg_attr(
7343673492
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73437-
assert_instr(trn)
73493+
assert_instr(trn1)
73494+
)]
73495+
#[cfg_attr(
73496+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73497+
assert_instr(trn2)
7343873498
)]
7343973499
#[cfg_attr(
7344073500
not(target_arch = "arm"),
@@ -73467,7 +73527,11 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
7346773527
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7346873528
#[cfg_attr(
7346973529
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73470-
assert_instr(trn)
73530+
assert_instr(trn1)
73531+
)]
73532+
#[cfg_attr(
73533+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73534+
assert_instr(trn2)
7347173535
)]
7347273536
#[cfg_attr(
7347373537
not(target_arch = "arm"),
@@ -73492,7 +73556,11 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
7349273556
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
7349373557
#[cfg_attr(
7349473558
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73495-
assert_instr(trn)
73559+
assert_instr(trn1)
73560+
)]
73561+
#[cfg_attr(
73562+
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73563+
assert_instr(trn2)
7349673564
)]
7349773565
#[cfg_attr(
7349873566
not(target_arch = "arm"),

‎library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9532,7 +9532,8 @@ intrinsics:
95329532
attr:
95339533
- *neon-v7
95349534
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
9535-
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn]]}]]
9535+
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn1]]}]]
9536+
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn2]]}]]
95369537
- *neon-not-arm-stable
95379538
- *neon-cfg-arm-unstable
95389539
safety: safe
@@ -9573,7 +9574,8 @@ intrinsics:
95739574
attr:
95749575
- *neon-v7
95759576
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
9576-
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn]]}]]
9577+
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn1]]}]]
9578+
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn2]]}]]
95779579
- *neon-fp16
95789580
- *neon-unstable-f16
95799581
safety: safe

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