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tesujitesuji
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Add MIPS asm! support
This patch also: * Add soft-float supports: only f32 * zero-extend i8/i16 to i32 because MIPS only supports register-length arithmetic. * Update table in asm! chapter in unstable book.
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5 files changed

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5 files changed

+389
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‎compiler/rustc_codegen_llvm/src/asm.rs‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
259259
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
260260
InlineAsmArch::Nvptx64 => {}
261261
InlineAsmArch::Hexagon => {}
262+
InlineAsmArch::Mips => {}
262263
}
263264
}
264265
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -505,6 +506,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
505506
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
506507
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
507508
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
509+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
510+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
508511
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
509512
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
510513
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
@@ -551,6 +554,7 @@ fn modifier_to_llvm(
551554
}
552555
}
553556
InlineAsmRegClass::Hexagon(_) => None,
557+
InlineAsmRegClass::Mips(_) => None,
554558
InlineAsmRegClass::Nvptx(_) => None,
555559
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
556560
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
@@ -603,6 +607,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
603607
cx.type_vector(cx.type_i64(), 2)
604608
}
605609
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
610+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
611+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
606612
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
607613
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
608614
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
@@ -700,6 +706,12 @@ fn llvm_fixup_input(
700706
value
701707
}
702708
}
709+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
710+
// MIPS only supports register-length arithmetics.
711+
Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
712+
Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
713+
_ => value,
714+
},
703715
_ => value,
704716
}
705717
}
@@ -768,6 +780,13 @@ fn llvm_fixup_output(
768780
value
769781
}
770782
}
783+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
784+
// MIPS only supports register-length arithmetics.
785+
Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
786+
Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
787+
Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
788+
_ => value,
789+
},
771790
_ => value,
772791
}
773792
}
@@ -831,6 +850,12 @@ fn llvm_fixup_output_type(
831850
layout.llvm_type(cx)
832851
}
833852
}
853+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
854+
// MIPS only supports register-length arithmetics.
855+
Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
856+
Primitive::F32 => cx.type_i32(),
857+
_ => layout.llvm_type(cx),
858+
},
834859
_ => layout.llvm_type(cx),
835860
}
836861
}

‎compiler/rustc_target/src/asm/mips.rs‎

Lines changed: 132 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
use std::fmt;
4+
5+
def_reg_class! {
6+
Mips MipsInlineAsmRegClass {
7+
reg,
8+
freg,
9+
}
10+
}
11+
12+
impl MipsInlineAsmRegClass {
13+
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
14+
&[]
15+
}
16+
17+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
18+
None
19+
}
20+
21+
pub fn suggest_modifier(
22+
self,
23+
_arch: InlineAsmArch,
24+
_ty: InlineAsmType,
25+
) -> Option<(char, &'static str)> {
26+
None
27+
}
28+
29+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
30+
None
31+
}
32+
33+
pub fn supported_types(
34+
self,
35+
_arch: InlineAsmArch,
36+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37+
match self {
38+
Self::reg => types! { _: I8, I16, I32, F32; },
39+
Self::freg => types! { _: F32; },
40+
}
41+
}
42+
}
43+
44+
// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
45+
def_regs! {
46+
Mips MipsInlineAsmReg MipsInlineAsmRegClass {
47+
v0: reg = ["$2", "$v0"],
48+
v1: reg = ["$3", "$v1"],
49+
a0: reg = ["$4", "$a0"],
50+
a1: reg = ["$5", "$a1"],
51+
a2: reg = ["$6", "$a2"],
52+
a3: reg = ["$7", "$a3"],
53+
// FIXME: Reserve $t0, $t1 if in mips16 mode.
54+
t0: reg = ["$8", "$t0"],
55+
t1: reg = ["$9", "$t1"],
56+
t2: reg = ["$10", "$t2"],
57+
t3: reg = ["$11", "$t3"],
58+
t4: reg = ["$12", "$t4"],
59+
t5: reg = ["$13", "$t5"],
60+
t6: reg = ["$14", "$t6"],
61+
t7: reg = ["$15", "$t7"],
62+
s0: reg = ["$16", "$s0"],
63+
s1: reg = ["$17", "$s1"],
64+
s2: reg = ["$18", "$s2"],
65+
s3: reg = ["$19", "$s3"],
66+
s4: reg = ["$20", "$s4"],
67+
s5: reg = ["$21", "$s5"],
68+
s6: reg = ["$22", "$s6"],
69+
s7: reg = ["$23", "$s7"],
70+
t8: reg = ["$24", "$t8"],
71+
t9: reg = ["$25", "$t9"],
72+
f0: freg = ["$f0"],
73+
f1: freg = ["$f1"],
74+
f2: freg = ["$f2"],
75+
f3: freg = ["$f3"],
76+
f4: freg = ["$f4"],
77+
f5: freg = ["$f5"],
78+
f6: freg = ["$f6"],
79+
f7: freg = ["$f7"],
80+
f8: freg = ["$f8"],
81+
f9: freg = ["$f9"],
82+
f10: freg = ["$f10"],
83+
f11: freg = ["$f11"],
84+
f12: freg = ["$f12"],
85+
f13: freg = ["$f13"],
86+
f14: freg = ["$f14"],
87+
f15: freg = ["$f15"],
88+
f16: freg = ["$f16"],
89+
f17: freg = ["$f17"],
90+
f18: freg = ["$f18"],
91+
f19: freg = ["$f19"],
92+
f20: freg = ["$f20"],
93+
f21: freg = ["$f21"],
94+
f22: freg = ["$f22"],
95+
f23: freg = ["$f23"],
96+
f24: freg = ["$f24"],
97+
f25: freg = ["$f25"],
98+
f26: freg = ["$f26"],
99+
f27: freg = ["$f27"],
100+
f28: freg = ["$f28"],
101+
f29: freg = ["$f29"],
102+
f30: freg = ["$f30"],
103+
f31: freg = ["$f31"],
104+
#error = ["$0", "$zero"] =>
105+
"constant zero cannot be used as an operand for inline asm",
106+
#error = ["$1", "$at"] =>
107+
"reserved for assembler (Assembler Temp)",
108+
#error = ["$26", "$k0"] =>
109+
"OS-reserved register cannot be used as an operand for inline asm",
110+
#error = ["$27", "$k1"] =>
111+
"OS-reserved register cannot be used as an operand for inline asm",
112+
#error = ["$28", "$gp"] =>
113+
"the global pointer cannot be used as an operand for inline asm",
114+
#error = ["$29", "$sp"] =>
115+
"the stack pointer cannot be used as an operand for inline asm",
116+
#error = ["$30", "$s8", "$fp"] =>
117+
"the frame pointer cannot be used as an operand for inline asm",
118+
#error = ["$31", "$ra"] =>
119+
"the return address register cannot be used as an operand for inline asm",
120+
}
121+
}
122+
123+
impl MipsInlineAsmReg {
124+
pub fn emit(
125+
self,
126+
out: &mut dyn fmt::Write,
127+
_arch: InlineAsmArch,
128+
_modifier: Option<char>,
129+
) -> fmt::Result {
130+
out.write_str(self.name())
131+
}
132+
}

‎compiler/rustc_target/src/asm/mod.rs‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -152,13 +152,15 @@ macro_rules! types {
152152
mod aarch64;
153153
mod arm;
154154
mod hexagon;
155+
mod mips;
155156
mod nvptx;
156157
mod riscv;
157158
mod x86;
158159

159160
pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
160161
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
161162
pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
163+
pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
162164
pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
163165
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
164166
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
@@ -173,6 +175,7 @@ pub enum InlineAsmArch {
173175
RiscV64,
174176
Nvptx64,
175177
Hexagon,
178+
Mips,
176179
}
177180

178181
impl FromStr for InlineAsmArch {
@@ -188,6 +191,7 @@ impl FromStr for InlineAsmArch {
188191
"riscv64" => Ok(Self::RiscV64),
189192
"nvptx64" => Ok(Self::Nvptx64),
190193
"hexagon" => Ok(Self::Hexagon),
194+
"mips" => Ok(Self::Mips),
191195
_ => Err(()),
192196
}
193197
}
@@ -201,6 +205,7 @@ pub enum InlineAsmReg {
201205
RiscV(RiscVInlineAsmReg),
202206
Nvptx(NvptxInlineAsmReg),
203207
Hexagon(HexagonInlineAsmReg),
208+
Mips(MipsInlineAsmReg),
204209
}
205210

206211
impl InlineAsmReg {
@@ -211,6 +216,7 @@ impl InlineAsmReg {
211216
Self::AArch64(r) => r.name(),
212217
Self::RiscV(r) => r.name(),
213218
Self::Hexagon(r) => r.name(),
219+
Self::Mips(r) => r.name(),
214220
}
215221
}
216222

@@ -221,6 +227,7 @@ impl InlineAsmReg {
221227
Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
222228
Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
223229
Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
230+
Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
224231
}
225232
}
226233

@@ -252,6 +259,9 @@ impl InlineAsmReg {
252259
InlineAsmArch::Hexagon => {
253260
Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
254261
}
262+
InlineAsmArch::Mips => {
263+
Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
264+
}
255265
})
256266
}
257267

@@ -269,6 +279,7 @@ impl InlineAsmReg {
269279
Self::AArch64(r) => r.emit(out, arch, modifier),
270280
Self::RiscV(r) => r.emit(out, arch, modifier),
271281
Self::Hexagon(r) => r.emit(out, arch, modifier),
282+
Self::Mips(r) => r.emit(out, arch, modifier),
272283
}
273284
}
274285

@@ -279,6 +290,7 @@ impl InlineAsmReg {
279290
Self::AArch64(_) => cb(self),
280291
Self::RiscV(_) => cb(self),
281292
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
293+
Self::Mips(_) => cb(self),
282294
}
283295
}
284296
}
@@ -291,6 +303,7 @@ pub enum InlineAsmRegClass {
291303
RiscV(RiscVInlineAsmRegClass),
292304
Nvptx(NvptxInlineAsmRegClass),
293305
Hexagon(HexagonInlineAsmRegClass),
306+
Mips(MipsInlineAsmRegClass),
294307
}
295308

296309
impl InlineAsmRegClass {
@@ -302,6 +315,7 @@ impl InlineAsmRegClass {
302315
Self::RiscV(r) => r.name(),
303316
Self::Nvptx(r) => r.name(),
304317
Self::Hexagon(r) => r.name(),
318+
Self::Mips(r) => r.name(),
305319
}
306320
}
307321

@@ -316,6 +330,7 @@ impl InlineAsmRegClass {
316330
Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
317331
Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
318332
Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
333+
Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
319334
}
320335
}
321336

@@ -337,6 +352,7 @@ impl InlineAsmRegClass {
337352
Self::RiscV(r) => r.suggest_modifier(arch, ty),
338353
Self::Nvptx(r) => r.suggest_modifier(arch, ty),
339354
Self::Hexagon(r) => r.suggest_modifier(arch, ty),
355+
Self::Mips(r) => r.suggest_modifier(arch, ty),
340356
}
341357
}
342358

@@ -354,6 +370,7 @@ impl InlineAsmRegClass {
354370
Self::RiscV(r) => r.default_modifier(arch),
355371
Self::Nvptx(r) => r.default_modifier(arch),
356372
Self::Hexagon(r) => r.default_modifier(arch),
373+
Self::Mips(r) => r.default_modifier(arch),
357374
}
358375
}
359376

@@ -370,6 +387,7 @@ impl InlineAsmRegClass {
370387
Self::RiscV(r) => r.supported_types(arch),
371388
Self::Nvptx(r) => r.supported_types(arch),
372389
Self::Hexagon(r) => r.supported_types(arch),
390+
Self::Mips(r) => r.supported_types(arch),
373391
}
374392
}
375393

@@ -391,6 +409,7 @@ impl InlineAsmRegClass {
391409
InlineAsmArch::Hexagon => {
392410
Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
393411
}
412+
InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
394413
})
395414
})
396415
}
@@ -405,6 +424,7 @@ impl InlineAsmRegClass {
405424
Self::RiscV(r) => r.valid_modifiers(arch),
406425
Self::Nvptx(r) => r.valid_modifiers(arch),
407426
Self::Hexagon(r) => r.valid_modifiers(arch),
427+
Self::Mips(r) => r.valid_modifiers(arch),
408428
}
409429
}
410430
}
@@ -545,5 +565,10 @@ pub fn allocatable_registers(
545565
hexagon::fill_reg_map(arch, has_feature, target, &mut map);
546566
map
547567
}
568+
InlineAsmArch::Mips => {
569+
let mut map = mips::regclass_map();
570+
mips::fill_reg_map(arch, has_feature, target, &mut map);
571+
map
572+
}
548573
}
549574
}

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