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AmanieuAmanieu
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Fix handling of reserved registers for ARM inline asm
1 parent 7adbc0d commit 8d0e882

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6 files changed

+67
-18
lines changed

6 files changed

+67
-18
lines changed

‎src/librustc_ast_lowering/expr.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1004,6 +1004,7 @@ impl<'hir> LoweringContext<'_, 'hir> {
10041004
asm::InlineAsmReg::parse(
10051005
sess.asm_arch?,
10061006
|feature| sess.target_features.contains(&Symbol::intern(feature)),
1007+
&sess.target.target,
10071008
s,
10081009
)
10091010
.map_err(|e| {

‎src/librustc_codegen_llvm/llvm_util.rs‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,10 @@ const ARM_WHITELIST: &[(&str, Option<Symbol>)] = &[
156156
("vfp2", Some(sym::arm_target_feature)),
157157
("vfp3", Some(sym::arm_target_feature)),
158158
("vfp4", Some(sym::arm_target_feature)),
159+
// This is needed for inline assembly, but shouldn't be stabilized as-is
160+
// since it should be enabled per-function using #[instruction_set], not
161+
// #[target_feature].
162+
("thumb-mode", Some(sym::arm_target_feature)),
159163
];
160164

161165
const AARCH64_WHITELIST: &[(&str, Option<Symbol>)] = &[

‎src/librustc_target/asm/arm.rs‎

Lines changed: 36 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
use super::{InlineAsmArch, InlineAsmType};
2+
use crate::spec::Target;
23
use rustc_macros::HashStable_Generic;
34
use std::fmt;
45

@@ -58,6 +59,37 @@ impl ArmInlineAsmRegClass {
5859
}
5960
}
6061

62+
// This uses the same logic as useR7AsFramePointer in LLVM
63+
fn frame_pointer_is_r7(mut has_feature: impl FnMut(&str) -> bool, target: &Target) -> bool {
64+
target.options.is_like_osx || (!target.options.is_like_windows && has_feature("thumb-mode"))
65+
}
66+
67+
fn frame_pointer_r11(
68+
_arch: InlineAsmArch,
69+
has_feature: impl FnMut(&str) -> bool,
70+
target: &Target,
71+
_allocating: bool,
72+
) -> Result<(), &'static str> {
73+
if !frame_pointer_is_r7(has_feature, target) {
74+
Err("the frame pointer (r11) cannot be used as an operand for inline asm")
75+
} else {
76+
Ok(())
77+
}
78+
}
79+
80+
fn frame_pointer_r7(
81+
_arch: InlineAsmArch,
82+
has_feature: impl FnMut(&str) -> bool,
83+
target: &Target,
84+
_allocating: bool,
85+
) -> Result<(), &'static str> {
86+
if frame_pointer_is_r7(has_feature, target) {
87+
Err("the frame pointer (r7) cannot be used as an operand for inline asm")
88+
} else {
89+
Ok(())
90+
}
91+
}
92+
6193
def_regs! {
6294
Arm ArmInlineAsmReg ArmInlineAsmRegClass {
6395
r0: reg, reg_thumb = ["r0", "a1"],
@@ -66,11 +98,11 @@ def_regs! {
6698
r3: reg, reg_thumb = ["r3", "a4"],
6799
r4: reg, reg_thumb = ["r4", "v1"],
68100
r5: reg, reg_thumb = ["r5", "v2"],
69-
r6: reg, reg_thumb = ["r6", "v3"],
70-
r7: reg, reg_thumb = ["r7", "v4"],
101+
r7: reg, reg_thumb = ["r7", "v4"] % frame_pointer_r7,
71102
r8: reg = ["r8", "v5"],
72103
r9: reg = ["r9", "v6", "rfp"],
73104
r10: reg = ["r10", "sl"],
105+
r11: reg = ["r11", "fp"] % frame_pointer_r11,
74106
r12: reg = ["r12", "ip"],
75107
r14: reg = ["r14", "lr"],
76108
s0: sreg, sreg_low16 = ["s0"],
@@ -153,8 +185,8 @@ def_regs! {
153185
q13: qreg = ["q13"],
154186
q14: qreg = ["q14"],
155187
q15: qreg = ["q15"],
156-
#error = ["r11", "fp"] =>
157-
"the frame pointer cannot be used as an operand for inline asm",
188+
#error = ["r6", "v3"] =>
189+
"r6 is used internally by LLVM and cannot be used as an operand for inline asm",
158190
#error = ["r13", "sp"] =>
159191
"the stack pointer cannot be used as an operand for inline asm",
160192
#error = ["r15", "pc"] =>

‎src/librustc_target/asm/mod.rs‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
use crate::abi::Size;
2+
use crate::spec::Target;
23
use rustc_data_structures::fx::{FxHashMap, FxHashSet};
34
use rustc_macros::HashStable_Generic;
45
use rustc_span::Symbol;
@@ -83,12 +84,13 @@ macro_rules! def_regs {
8384
pub fn parse(
8485
_arch: super::InlineAsmArch,
8586
mut _has_feature: impl FnMut(&str) -> bool,
87+
_target: &crate::spec::Target,
8688
name: &str,
8789
) -> Result<Self, &'static str> {
8890
match name {
8991
$(
9092
$($alias)|* | $reg_name => {
91-
$($filter(_arch, &mut _has_feature, false)?;)?
93+
$($filter(_arch, &mut _has_feature, _target, false)?;)?
9294
Ok(Self::$reg)
9395
}
9496
)*
@@ -103,6 +105,7 @@ macro_rules! def_regs {
103105
pub(super) fn fill_reg_map(
104106
_arch: super::InlineAsmArch,
105107
mut _has_feature: impl FnMut(&str) -> bool,
108+
_target: &crate::spec::Target,
106109
_map: &mut rustc_data_structures::fx::FxHashMap<
107110
super::InlineAsmRegClass,
108111
rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
@@ -111,7 +114,7 @@ macro_rules! def_regs {
111114
#[allow(unused_imports)]
112115
use super::{InlineAsmReg, InlineAsmRegClass};
113116
$(
114-
if $($filter(_arch, &mut _has_feature, true).is_ok() &&)? true {
117+
if $($filter(_arch, &mut _has_feature, _target, true).is_ok() &&)? true {
115118
if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
116119
set.insert(InlineAsmReg::$arch($arch_reg::$reg));
117120
}
@@ -234,27 +237,30 @@ impl InlineAsmReg {
234237
pub fn parse(
235238
arch: InlineAsmArch,
236239
has_feature: impl FnMut(&str) -> bool,
240+
target: &Target,
237241
name: Symbol,
238242
) -> Result<Self, &'static str> {
239243
// FIXME: use direct symbol comparison for register names
240244
// Use `Symbol::as_str` instead of `Symbol::with` here because `has_feature` may access `Symbol`.
241245
let name = name.as_str();
242246
Ok(match arch {
243247
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
244-
Self::X86(X86InlineAsmReg::parse(arch, has_feature, &name)?)
248+
Self::X86(X86InlineAsmReg::parse(arch, has_feature, target, &name)?)
249+
}
250+
InlineAsmArch::Arm => {
251+
Self::Arm(ArmInlineAsmReg::parse(arch, has_feature, target, &name)?)
245252
}
246-
InlineAsmArch::Arm => Self::Arm(ArmInlineAsmReg::parse(arch, has_feature, &name)?),
247253
InlineAsmArch::AArch64 => {
248-
Self::AArch64(AArch64InlineAsmReg::parse(arch, has_feature, &name)?)
254+
Self::AArch64(AArch64InlineAsmReg::parse(arch, has_feature, target, &name)?)
249255
}
250256
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
251-
Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, &name)?)
257+
Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, target, &name)?)
252258
}
253259
InlineAsmArch::Nvptx64 => {
254-
Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, &name)?)
260+
Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, target, &name)?)
255261
}
256262
InlineAsmArch::Hexagon => {
257-
Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, &name)?)
263+
Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
258264
}
259265
})
260266
}
@@ -536,36 +542,37 @@ impl fmt::Display for InlineAsmType {
536542
pub fn allocatable_registers(
537543
arch: InlineAsmArch,
538544
has_feature: impl FnMut(&str) -> bool,
545+
target: &crate::spec::Target,
539546
) -> FxHashMap<InlineAsmRegClass, FxHashSet<InlineAsmReg>> {
540547
match arch {
541548
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
542549
let mut map = x86::regclass_map();
543-
x86::fill_reg_map(arch, has_feature, &mut map);
550+
x86::fill_reg_map(arch, has_feature, target, &mut map);
544551
map
545552
}
546553
InlineAsmArch::Arm => {
547554
let mut map = arm::regclass_map();
548-
arm::fill_reg_map(arch, has_feature, &mut map);
555+
arm::fill_reg_map(arch, has_feature, target, &mut map);
549556
map
550557
}
551558
InlineAsmArch::AArch64 => {
552559
let mut map = aarch64::regclass_map();
553-
aarch64::fill_reg_map(arch, has_feature, &mut map);
560+
aarch64::fill_reg_map(arch, has_feature, target, &mut map);
554561
map
555562
}
556563
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
557564
let mut map = riscv::regclass_map();
558-
riscv::fill_reg_map(arch, has_feature, &mut map);
565+
riscv::fill_reg_map(arch, has_feature, target, &mut map);
559566
map
560567
}
561568
InlineAsmArch::Nvptx64 => {
562569
let mut map = nvptx::regclass_map();
563-
nvptx::fill_reg_map(arch, has_feature, &mut map);
570+
nvptx::fill_reg_map(arch, has_feature, target, &mut map);
564571
map
565572
}
566573
InlineAsmArch::Hexagon => {
567574
let mut map = hexagon::regclass_map();
568-
hexagon::fill_reg_map(arch, has_feature, &mut map);
575+
hexagon::fill_reg_map(arch, has_feature, target, &mut map);
569576
map
570577
}
571578
}

‎src/librustc_target/asm/riscv.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
use super::{InlineAsmArch, InlineAsmType};
2+
use crate::spec::Target;
23
use rustc_macros::HashStable_Generic;
34
use std::fmt;
45

@@ -50,6 +51,7 @@ impl RiscVInlineAsmRegClass {
5051
fn not_e(
5152
_arch: InlineAsmArch,
5253
mut has_feature: impl FnMut(&str) -> bool,
54+
_target: &Target,
5355
_allocating: bool,
5456
) -> Result<(), &'static str> {
5557
if has_feature("e") {

‎src/librustc_target/asm/x86.rs‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
use super::{InlineAsmArch, InlineAsmType};
2+
use crate::spec::Target;
23
use rustc_macros::HashStable_Generic;
34
use std::fmt;
45

@@ -131,6 +132,7 @@ impl X86InlineAsmRegClass {
131132
fn x86_64_only(
132133
arch: InlineAsmArch,
133134
_has_feature: impl FnMut(&str) -> bool,
135+
_target: &Target,
134136
_allocating: bool,
135137
) -> Result<(), &'static str> {
136138
match arch {
@@ -143,6 +145,7 @@ fn x86_64_only(
143145
fn high_byte(
144146
arch: InlineAsmArch,
145147
_has_feature: impl FnMut(&str) -> bool,
148+
_target: &Target,
146149
allocating: bool,
147150
) -> Result<(), &'static str> {
148151
match arch {

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