ignore array.size() <= 16 bytes

Author: tesuji

compiler/rustc_mir_transform/src/gvn.rs

@@ -366,7 +366,12 @@ impl<'body, 'tcx> VnState<'body, 'tcx> {
 
     #[instrument(level = "trace", skip(self), ret)]
     fn eval_to_const(&mut self, value: VnIndex) -> Option<OpTy<'tcx>> {
+        use abi::HasDataLayout;
         use Value::*;
+        // LLVM optimizes the load of `sizeof(size_t) * 2` as a single `mov`,
+        // which is cheap. Bigger values make more `mov` instructions generated.
+        // After GVN, it becomes a single load (`lea`) of an address in `.rodata`.
+        let stack_threshold = self.tcx.data_layout().pointer_size * 2;
         let vvalue = self.get(value);
         debug!(?vvalue);
         let op = match *vvalue {
@@ -411,6 +416,9 @@ impl<'body, 'tcx> VnState<'body, 'tcx> {
                     let ptr_imm = Immediate::new_pointer_with_meta(data, meta, &self.ecx);
                     ImmTy::from_immediate(ptr_imm, ty).into()
                 } else if matches!(kind, AggregateTy::Array) {
+                    if ty.layout.size() <= stack_threshold {
+                        return None;
+                    }
                     let mut mplace = None;
                     let alloc_id = self
                         .ecx

tests/mir-opt/const_array_locals.main.GVN.diff

@@ -81,16 +81,12 @@
           StorageDead(_12);
           StorageLive(_13);
           StorageLive(_14);
--         _14 = [const 1_i32, const 0_i32, const 0_i32];
-+         _14 = const [1_i32, 0_i32, 0_i32];
+          _14 = [const 1_i32, const 0_i32, const 0_i32];
           StorageLive(_15);
--         _15 = [const 0_i32, const 1_i32, const 0_i32];
-+         _15 = const [0_i32, 1_i32, 0_i32];
+          _15 = [const 0_i32, const 1_i32, const 0_i32];
           StorageLive(_16);
--         _16 = [const 0_i32, const 0_i32, const 1_i32];
--         _13 = [move _14, move _15, move _16];
-+         _16 = const [0_i32, 0_i32, 1_i32];
-+         _13 = [const [1_i32, 0_i32, 0_i32], const [0_i32, 1_i32, 0_i32], const [0_i32, 0_i32, 1_i32]];
+          _16 = [const 0_i32, const 0_i32, const 1_i32];
+          _13 = [move _14, move _15, move _16];
           StorageDead(_16);
           StorageDead(_15);
           StorageDead(_14);
@@ -105,43 +101,31 @@
       }
 + }
 + 
-+ ALLOC0 (size: 12, align: 4) {
-+     00 00 00 00 00 00 00 00 01 00 00 00             │ ............
-+ }
-+ 
-+ ALLOC1 (size: 12, align: 4) {
-+     00 00 00 00 01 00 00 00 00 00 00 00             │ ............
-+ }
-+ 
-+ ALLOC2 (size: 12, align: 4) {
-+     01 00 00 00 00 00 00 00 00 00 00 00             │ ............
-+ }
-+ 
-+ ALLOC3 (size: 32, align: 4) {
++ ALLOC0 (size: 32, align: 4) {
 +     0x00 │ 00 00 80 3f 00 00 00 40 00 00 40 40 00 00 80 3f │ ...?...@..@@...?
 +     0x10 │ 00 00 80 3f 00 00 80 3f 00 00 80 3f 00 00 28 42 │ ...?...?...?..(B
 + }
 + 
-+ ALLOC4 (size: 64, align: 2) {
++ ALLOC1 (size: 64, align: 2) {
 +     0x00 │ ff 00 69 00 0f 00 27 00 3e 00 fb 00 bf 00 b2 00 │ ..i...'.>.......
 +     0x10 │ 09 00 04 00 38 00 dd 00 c1 00 a4 00 c2 00 c5 00 │ ....8...........
 +     0x20 │ 06 00 f3 00 da 00 ab 00 57 00 f7 00 68 00 9f 00 │ ........W...h...
 +     0x30 │ 16 00 9d 00 69 00 1f 00 60 00 ad 00 32 00 01 00 │ ....i...`...2...
 + }
 + 
-+ ALLOC5 (size: 48, align: 4) {
++ ALLOC2 (size: 48, align: 4) {
 +     0x00 │ c1 00 00 00 a4 00 00 00 c2 00 00 00 c5 00 00 00 │ ................
 +     0x10 │ 06 00 00 00 f3 00 00 00 da 00 00 00 ab 00 00 00 │ ................
 +     0x20 │ 57 00 00 00 f7 00 00 00 68 00 00 00 2a 00 00 00 │ W.......h...*...
 + }
 + 
-+ ALLOC6 (size: 48, align: 4) {
++ ALLOC3 (size: 48, align: 4) {
 +     0x00 │ ff 00 00 00 69 00 00 00 0f 00 00 00 27 00 00 00 │ ....i.......'...
 +     0x10 │ 3e 00 00 00 fb 00 00 00 bf 00 00 00 b2 00 00 00 │ >...............
 +     0x20 │ 09 00 00 00 04 00 00 00 38 00 00 00 dd 00 00 00 │ ........8.......
 + }
 + 
-+ ALLOC7 (size: 128, align: 4) {
++ ALLOC4 (size: 128, align: 4) {
 +     0x00 │ ff 00 00 00 69 00 00 00 0f 00 00 00 27 00 00 00 │ ....i.......'...
 +     0x10 │ 3e 00 00 00 fb 00 00 00 bf 00 00 00 b2 00 00 00 │ >...............
 +     0x20 │ 09 00 00 00 04 00 00 00 38 00 00 00 dd 00 00 00 │ ........8.......

tests/mir-opt/const_prop/array_index.main.GVN.64bit.panic-unwind.diff

@@ -15,8 +15,7 @@
       bb0: {
           StorageLive(_1);
           StorageLive(_2);
--         _2 = [const 0_u32, const 1_u32, const 2_u32, const 3_u32];
-+         _2 = const [0_u32, 1_u32, 2_u32, 3_u32];
+          _2 = [const 0_u32, const 1_u32, const 2_u32, const 3_u32];
           StorageLive(_3);
           _3 = const 2_usize;
 -         _4 = Len(_2);
@@ -36,9 +35,5 @@
           StorageDead(_1);
           return;
       }
-+ }
-+ 
-+ ALLOC0 (size: 16, align: 4) {
-+     00 00 00 00 01 00 00 00 02 00 00 00 03 00 00 00 │ ................
   }