Using def_path to fix tests.

Author: ywxt

compiler/rustc_middle/src/mir/mono.rs

@@ -525,12 +525,20 @@ impl<'tcx> CodegenUnit<'tcx> {
         tcx: TyCtxt<'tcx>,
     ) -> Vec<(MonoItem<'tcx>, MonoItemData)> {
         // The codegen tests rely on items being process in the same order as
-        // they appear in the file, so for local items, we sort by span first
+        // they appear in the file, so for local items, we sort by span and def_path first
         #[derive(PartialEq, Eq, PartialOrd, Ord)]
-        struct ItemSortKey<'tcx>(Option<Span>, SymbolName<'tcx>);
+        struct ItemSortKey<'tcx>(Option<Span>, Option<String>, SymbolName<'tcx>);
 
         fn item_sort_key<'tcx>(tcx: TyCtxt<'tcx>, item: MonoItem<'tcx>) -> ItemSortKey<'tcx> {
-            ItemSortKey(item.local_span(tcx), item.symbol_name(tcx))
+            ItemSortKey(
+                // For codegen tests purposes, we don't care about non-local items' order,
+                // so we just sort non-local items by symbol names.
+                item.local_span(tcx),
+                item.def_id()
+                    .as_local()
+                    .map(|_| tcx.def_path(item.def_id()).to_string_no_crate_verbose()),
+                item.symbol_name(tcx),
+            )
         }
 
         let mut items: Vec<_> = self.items().iter().map(|(&i, &data)| (i, data)).collect();

src/tools/compiletest/src/runtest/assembly.rs

@@ -42,7 +42,6 @@ impl TestCx<'_> {
             LinkToAux::Yes,
             Vec::new(),
         );
-
         let proc_res = self.compose_and_run_compiler(rustc, None, self.testpaths);
         (proc_res, output_path)
     }

tests/assembly-llvm/asm/aarch64-modifiers.rs

@@ -55,35 +55,17 @@ check!(vreg vreg "add {0}.4s, {0}.4s, {0}.4s");
 // CHECK: //NO_APP
 check!(vreg_b vreg "ldr {:b}, [x0]");
 
-// CHECK-LABEL: vreg_h:
-// CHECK: //APP
-// CHECK: ldr h0, [x0]
-// CHECK: //NO_APP
-check!(vreg_h vreg "ldr {:h}, [x0]");
-
-// CHECK-LABEL: vreg_s:
-// CHECK: //APP
-// CHECK: ldr s0, [x0]
-// CHECK: //NO_APP
-check!(vreg_s vreg "ldr {:s}, [x0]");
-
 // CHECK-LABEL: vreg_d:
 // CHECK: //APP
 // CHECK: ldr d0, [x0]
 // CHECK: //NO_APP
 check!(vreg_d vreg "ldr {:d}, [x0]");
 
-// CHECK-LABEL: vreg_q:
-// CHECK: //APP
-// CHECK: ldr q0, [x0]
-// CHECK: //NO_APP
-check!(vreg_q vreg "ldr {:q}, [x0]");
-
-// CHECK-LABEL: vreg_v:
+// CHECK-LABEL: vreg_h:
 // CHECK: //APP
-// CHECK: add v0.4s, v0.4s, v0.4s
+// CHECK: ldr h0, [x0]
 // CHECK: //NO_APP
-check!(vreg_v vreg "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
+check!(vreg_h vreg "ldr {:h}, [x0]");
 
 // CHECK-LABEL: vreg_low16:
 // CHECK: //APP
@@ -97,32 +79,50 @@ check!(vreg_low16 vreg_low16 "add {0}.4s, {0}.4s, {0}.4s");
 // CHECK: //NO_APP
 check!(vreg_low16_b vreg_low16 "ldr {:b}, [x0]");
 
+// CHECK-LABEL: vreg_low16_d:
+// CHECK: //APP
+// CHECK: ldr d0, [x0]
+// CHECK: //NO_APP
+check!(vreg_low16_d vreg_low16 "ldr {:d}, [x0]");
+
 // CHECK-LABEL: vreg_low16_h:
 // CHECK: //APP
 // CHECK: ldr h0, [x0]
 // CHECK: //NO_APP
 check!(vreg_low16_h vreg_low16 "ldr {:h}, [x0]");
 
+// CHECK-LABEL: vreg_low16_q:
+// CHECK: //APP
+// CHECK: ldr q0, [x0]
+// CHECK: //NO_APP
+check!(vreg_low16_q vreg_low16 "ldr {:q}, [x0]");
+
 // CHECK-LABEL: vreg_low16_s:
 // CHECK: //APP
 // CHECK: ldr s0, [x0]
 // CHECK: //NO_APP
 check!(vreg_low16_s vreg_low16 "ldr {:s}, [x0]");
 
-// CHECK-LABEL: vreg_low16_d:
+// CHECK-LABEL: vreg_low16_v:
 // CHECK: //APP
-// CHECK: ldr d0, [x0]
+// CHECK: add v0.4s, v0.4s, v0.4s
 // CHECK: //NO_APP
-check!(vreg_low16_d vreg_low16 "ldr {:d}, [x0]");
+check!(vreg_low16_v vreg_low16 "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
 
-// CHECK-LABEL: vreg_low16_q:
+// CHECK-LABEL: vreg_q:
 // CHECK: //APP
 // CHECK: ldr q0, [x0]
 // CHECK: //NO_APP
-check!(vreg_low16_q vreg_low16 "ldr {:q}, [x0]");
+check!(vreg_q vreg "ldr {:q}, [x0]");
 
-// CHECK-LABEL: vreg_low16_v:
+// CHECK-LABEL: vreg_s:
+// CHECK: //APP
+// CHECK: ldr s0, [x0]
+// CHECK: //NO_APP
+check!(vreg_s vreg "ldr {:s}, [x0]");
+
+// CHECK-LABEL: vreg_v:
 // CHECK: //APP
 // CHECK: add v0.4s, v0.4s, v0.4s
 // CHECK: //NO_APP
-check!(vreg_low16_v vreg_low16 "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
+check!(vreg_v vreg "add {0:v}.4s, {0:v}.4s, {0:v}.4s");