feat: Add no_std Xtensa targets support

Author: SergioGasquez

compiler/rustc_target/src/spec/base/mod.rs

@@ -35,3 +35,4 @@ pub(crate) mod windows_gnullvm;
 pub(crate) mod windows_msvc;
 pub(crate) mod windows_uwp_gnu;
 pub(crate) mod windows_uwp_msvc;
+pub(crate) mod xtensa;

compiler/rustc_target/src/spec/base/xtensa.rs

@@ -0,0 +1,17 @@
+use crate::abi::Endian;
+use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, TargetOptions};
+
+pub fn opts() -> TargetOptions {
+    TargetOptions {
+        os: "none".into(),
+        endian: Endian::Little,
+        c_int_width: "32".into(),
+        linker_flavor: LinkerFlavor::Gnu(Cc::Yes, Lld::No),
+        executables: true,
+        panic_strategy: PanicStrategy::Abort,
+        relocation_model: RelocModel::Static,
+        emit_debug_gdb_scripts: false,
+        atomic_cas: false,
+        ..Default::default()
+    }
+}

compiler/rustc_target/src/spec/mod.rs

@@ -1725,6 +1725,10 @@ supported_targets! {
 
     ("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
 
+    ("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
+    ("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
+    ("xtensa-esp32s3-none-elf", xtensa_esp32s3_none_elf),
+
     ("i686-wrs-vxworks", i686_wrs_vxworks),
     ("x86_64-wrs-vxworks", x86_64_wrs_vxworks),
     ("armv7-wrs-vxworks-eabihf", armv7_wrs_vxworks_eabihf),

compiler/rustc_target/src/spec/targets/xtensa_esp32_none_elf.rs

@@ -0,0 +1,24 @@
+use crate::spec::{base::xtensa, Target, TargetOptions};
+
+pub fn target() -> Target {
+    Target {
+        llvm_target: "xtensa-none-elf".into(),
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
+        arch: "xtensa".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: None,
+            host_tools: None,
+            std: None,
+        },
+
+        options: TargetOptions {
+            cpu: "esp32".into(),
+            linker: Some("xtensa-esp32-elf-gcc".into()),
+            max_atomic_width: Some(32),
+            atomic_cas: true,
+            ..xtensa::opts()
+        },
+    }
+}

compiler/rustc_target/src/spec/targets/xtensa_esp32s2_none_elf.rs

@@ -0,0 +1,23 @@
+use crate::spec::{base::xtensa, Target, TargetOptions};
+
+pub fn target() -> Target {
+    Target {
+        llvm_target: "xtensa-none-elf".into(),
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
+        arch: "xtensa".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: None,
+            host_tools: None,
+            std: None,
+        },
+
+        options: TargetOptions {
+            cpu: "esp32-s2".into(),
+            linker: Some("xtensa-esp32s2-elf-gcc".into()),
+            max_atomic_width: Some(32),
+            ..xtensa::opts()
+        },
+    }
+}

compiler/rustc_target/src/spec/targets/xtensa_esp32s3_none_elf.rs

@@ -0,0 +1,24 @@
+use crate::spec::{base::xtensa, Target, TargetOptions};
+
+pub fn target() -> Target {
+    Target {
+        llvm_target: "xtensa-none-elf".into(),
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
+        arch: "xtensa".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: None,
+            tier: None,
+            host_tools: None,
+            std: None,
+        },
+
+        options: TargetOptions {
+            cpu: "esp32-s3".into(),
+            linker: Some("xtensa-esp32s3-elf-gcc".into()),
+            max_atomic_width: Some(32),
+            atomic_cas: true,
+            ..xtensa::opts()
+        },
+    }
+}

src/doc/rustc/src/platform-support.md

@@ -383,5 +383,8 @@ target | std | host | notes
 `x86_64-wrs-vxworks` | ? |  |
 [`x86_64h-apple-darwin`](platform-support/x86_64h-apple-darwin.md) | ✓ | ✓ | macOS with late-gen Intel (at least Haswell)
 [`x86_64-unknown-linux-none`](platform-support/x86_64-unknown-linux-none.md) | * |  | 64-bit Linux with no libc
+`xtensa-esp32-none-elf` |  |  | Xtensa ESP32
+`xtensa-esp32s2-none-elf` |  |  | Xtensa ESP32-S2
+`xtensa-esp32s3-none-elf` |  |  | Xtensa ESP32-S3
 
 [runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets

src/doc/rustc/src/platform-support/xtensa.md

@@ -0,0 +1,25 @@
+# `xtensa-*`
+
+**Tier: 3**
+
+Targets for Xtensa CPUs.
+
+## Target maintainers
+
+- Scott Mabin [@MabezDev](https://github.com/MabezDev)
+- Sergio Gasquez [@SergioGasquez](https://github.com/SergioGasquez)
+
+## Requirements
+
+The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined:
+
+| Target name               | Target CPU(s)                                                   |
+| ------------------------- | --------------------------------------------------------------- |
+| `xtensa-esp32-none-elf`   | [ESP32](https://www.espressif.com/en/products/socs/esp32)       |
+| `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
+| `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
+
+
+## Building the target
+
+The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of the The Rust on ESP Book](https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html).