Skip to content

Commit 1aa0192

Browse files
jieyouxujieyouxu
authored
Rollup merge of #131551 - taiki-e:ppc-asm-vreg-inout, r=Amanieu
Support input/output in vector registers of PowerPC inline assembly This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types as input/output. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | PowerPC | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` | | PowerPC | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` | In addition to floats and `core::simd` types listed above, `core::arch` types and custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types and relevant target features are currently unstable. r? `@Amanieu` `@rustbot` label +O-PowerPC +A-inline-assembly
2 parents 76f3ff6 + df8feb5 commit 1aa0192

File tree

12 files changed

+703
-352
lines changed

12 files changed

+703
-352
lines changed

‎compiler/rustc_codegen_gcc/src/asm.rs‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -656,9 +656,9 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
656656
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => "r",
657657
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
658658
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
659+
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => "v",
659660
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
660-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer)
661-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => {
661+
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
662662
unreachable!("clobber-only")
663663
}
664664
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => "r",
@@ -736,9 +736,11 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
736736
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
737737
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
738738
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
739+
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => {
740+
cx.type_vector(cx.type_i32(), 4)
741+
}
739742
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::cr)
740-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer)
741-
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vreg) => {
743+
| InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::xer) => {
742744
unreachable!("clobber-only")
743745
}
744746
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),

‎compiler/rustc_codegen_llvm/src/asm.rs‎

Lines changed: 46 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -656,9 +656,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
656656
PowerPC(PowerPCInlineAsmRegClass::reg) => "r",
657657
PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => "b",
658658
PowerPC(PowerPCInlineAsmRegClass::freg) => "f",
659-
PowerPC(PowerPCInlineAsmRegClass::cr)
660-
| PowerPC(PowerPCInlineAsmRegClass::xer)
661-
| PowerPC(PowerPCInlineAsmRegClass::vreg) => {
659+
PowerPC(PowerPCInlineAsmRegClass::vreg) => "v",
660+
PowerPC(PowerPCInlineAsmRegClass::cr) | PowerPC(PowerPCInlineAsmRegClass::xer) => {
662661
unreachable!("clobber-only")
663662
}
664663
RiscV(RiscVInlineAsmRegClass::reg) => "r",
@@ -825,9 +824,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
825824
PowerPC(PowerPCInlineAsmRegClass::reg) => cx.type_i32(),
826825
PowerPC(PowerPCInlineAsmRegClass::reg_nonzero) => cx.type_i32(),
827826
PowerPC(PowerPCInlineAsmRegClass::freg) => cx.type_f64(),
828-
PowerPC(PowerPCInlineAsmRegClass::cr)
829-
| PowerPC(PowerPCInlineAsmRegClass::xer)
830-
| PowerPC(PowerPCInlineAsmRegClass::vreg) => {
827+
PowerPC(PowerPCInlineAsmRegClass::vreg) => cx.type_vector(cx.type_i32(), 4),
828+
PowerPC(PowerPCInlineAsmRegClass::cr) | PowerPC(PowerPCInlineAsmRegClass::xer) => {
831829
unreachable!("clobber-only")
832830
}
833831
RiscV(RiscVInlineAsmRegClass::reg) => cx.type_i32(),
@@ -1042,6 +1040,26 @@ fn llvm_fixup_input<'ll, 'tcx>(
10421040
let value = bx.or(value, bx.const_u32(0xFFFF_0000));
10431041
bx.bitcast(value, bx.type_f32())
10441042
}
1043+
(PowerPC(PowerPCInlineAsmRegClass::vreg), BackendRepr::Scalar(s))
1044+
if s.primitive() == Primitive::Float(Float::F32) =>
1045+
{
1046+
let value = bx.insert_element(
1047+
bx.const_undef(bx.type_vector(bx.type_f32(), 4)),
1048+
value,
1049+
bx.const_usize(0),
1050+
);
1051+
bx.bitcast(value, bx.type_vector(bx.type_f32(), 4))
1052+
}
1053+
(PowerPC(PowerPCInlineAsmRegClass::vreg), BackendRepr::Scalar(s))
1054+
if s.primitive() == Primitive::Float(Float::F64) =>
1055+
{
1056+
let value = bx.insert_element(
1057+
bx.const_undef(bx.type_vector(bx.type_f64(), 2)),
1058+
value,
1059+
bx.const_usize(0),
1060+
);
1061+
bx.bitcast(value, bx.type_vector(bx.type_f64(), 2))
1062+
}
10451063
_ => value,
10461064
}
10471065
}
@@ -1177,6 +1195,18 @@ fn llvm_fixup_output<'ll, 'tcx>(
11771195
let value = bx.trunc(value, bx.type_i16());
11781196
bx.bitcast(value, bx.type_f16())
11791197
}
1198+
(PowerPC(PowerPCInlineAsmRegClass::vreg), BackendRepr::Scalar(s))
1199+
if s.primitive() == Primitive::Float(Float::F32) =>
1200+
{
1201+
let value = bx.bitcast(value, bx.type_vector(bx.type_f32(), 4));
1202+
bx.extract_element(value, bx.const_usize(0))
1203+
}
1204+
(PowerPC(PowerPCInlineAsmRegClass::vreg), BackendRepr::Scalar(s))
1205+
if s.primitive() == Primitive::Float(Float::F64) =>
1206+
{
1207+
let value = bx.bitcast(value, bx.type_vector(bx.type_f64(), 2));
1208+
bx.extract_element(value, bx.const_usize(0))
1209+
}
11801210
_ => value,
11811211
}
11821212
}
@@ -1301,6 +1331,16 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
13011331
{
13021332
cx.type_f32()
13031333
}
1334+
(PowerPC(PowerPCInlineAsmRegClass::vreg), BackendRepr::Scalar(s))
1335+
if s.primitive() == Primitive::Float(Float::F32) =>
1336+
{
1337+
cx.type_vector(cx.type_f32(), 4)
1338+
}
1339+
(PowerPC(PowerPCInlineAsmRegClass::vreg), BackendRepr::Scalar(s))
1340+
if s.primitive() == Primitive::Float(Float::F64) =>
1341+
{
1342+
cx.type_vector(cx.type_f64(), 2)
1343+
}
13041344
_ => layout.llvm_type(cx),
13051345
}
13061346
}

‎compiler/rustc_span/src/symbol.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -392,6 +392,7 @@ symbols! {
392392
allow_fail,
393393
allow_internal_unsafe,
394394
allow_internal_unstable,
395+
altivec,
395396
alu32,
396397
always,
397398
and,
@@ -2154,6 +2155,7 @@ symbols! {
21542155
volatile_store,
21552156
vreg,
21562157
vreg_low16,
2158+
vsx,
21572159
vtable_align,
21582160
vtable_size,
21592161
warn,

‎compiler/rustc_target/src/asm/powerpc.rs‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,11 @@ impl PowerPCInlineAsmRegClass {
5151
}
5252
}
5353
Self::freg => types! { _: F32, F64; },
54-
Self::vreg => &[],
54+
// FIXME: vsx also supports integers?: https://github.com/rust-lang/rust/pull/131551#discussion_r1862535963
55+
Self::vreg => types! {
56+
altivec: VecI8(16), VecI16(8), VecI32(4), VecF32(4);
57+
vsx: F32, F64, VecI64(2), VecF64(2);
58+
},
5559
Self::cr | Self::xer => &[],
5660
}
5761
}

‎src/doc/unstable-book/src/language-features/asm-experimental-arch.md‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
3434
| PowerPC | `reg` | `r0`, `r[3-12]`, `r[14-28]` | `r` |
3535
| PowerPC | `reg_nonzero` | `r[3-12]`, `r[14-28]` | `b` |
3636
| PowerPC | `freg` | `f[0-31]` | `f` |
37-
| PowerPC | `vreg` | `v[0-31]` | Only clobbers |
37+
| PowerPC | `vreg` | `v[0-31]` | `v` |
3838
| PowerPC | `cr` | `cr[0-7]`, `cr` | Only clobbers |
3939
| PowerPC | `xer` | `xer` | Only clobbers |
4040
| wasm32 | `local` | None\* | `r` |
@@ -75,7 +75,8 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
7575
| PowerPC | `reg` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
7676
| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
7777
| PowerPC | `freg` | None | `f32`, `f64` |
78-
| PowerPC | `vreg` | N/A | Only clobbers |
78+
| PowerPC | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` |
79+
| PowerPC | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` |
7980
| PowerPC | `cr` | N/A | Only clobbers |
8081
| PowerPC | `xer` | N/A | Only clobbers |
8182
| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
@@ -181,6 +182,7 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
181182
| PowerPC | `reg` | None | `0` | None |
182183
| PowerPC | `reg_nonzero` | None | `3` | None |
183184
| PowerPC | `freg` | None | `0` | None |
185+
| PowerPC | `vreg` | None | `0` | None |
184186
| SPARC | `reg` | None | `%o0` | None |
185187
| CSKY | `reg` | None | `r0` | None |
186188
| CSKY | `freg` | None | `f0` | None |

0 commit comments

Comments
 (0)