@@ -11,30 +11,30 @@ macro_rules! impl_integer_reductions {
1111 where
1212 LaneCount <LANES >: SupportedLaneCount ,
1313 {
14- /// Horizontal wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
14+ /// Reducing wrapping add. Returns the sum of the lanes of the vector, with wrapping addition.
1515 #[ inline]
16- pub fn horizontal_sum ( self ) -> $scalar {
16+ pub fn reduce_sum ( self ) -> $scalar {
1717 // Safety: `self` is an integer vector
1818 unsafe { simd_reduce_add_ordered( self , 0 ) }
1919 }
2020
21- /// Horizontal wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
21+ /// Reducing wrapping multiply. Returns the product of the lanes of the vector, with wrapping multiplication.
2222 #[ inline]
23- pub fn horizontal_product ( self ) -> $scalar {
23+ pub fn reduce_product ( self ) -> $scalar {
2424 // Safety: `self` is an integer vector
2525 unsafe { simd_reduce_mul_ordered( self , 1 ) }
2626 }
2727
28- /// Horizontal maximum. Returns the maximum lane in the vector.
28+ /// Reducing maximum. Returns the maximum lane in the vector.
2929 #[ inline]
30- pub fn horizontal_max ( self ) -> $scalar {
30+ pub fn reduce_max ( self ) -> $scalar {
3131 // Safety: `self` is an integer vector
3232 unsafe { simd_reduce_max( self ) }
3333 }
3434
35- /// Horizontal minimum. Returns the minimum lane in the vector.
35+ /// Reducing minimum. Returns the minimum lane in the vector.
3636 #[ inline]
37- pub fn horizontal_min ( self ) -> $scalar {
37+ pub fn reduce_min ( self ) -> $scalar {
3838 // Safety: `self` is an integer vector
3939 unsafe { simd_reduce_min( self ) }
4040 }
@@ -60,9 +60,9 @@ macro_rules! impl_float_reductions {
6060 LaneCount <LANES >: SupportedLaneCount ,
6161 {
6262
63- /// Horizontal add. Returns the sum of the lanes of the vector.
63+ /// Reducing add. Returns the sum of the lanes of the vector.
6464 #[ inline]
65- pub fn horizontal_sum ( self ) -> $scalar {
65+ pub fn reduce_sum ( self ) -> $scalar {
6666 // LLVM sum is inaccurate on i586
6767 if cfg!( all( target_arch = "x86" , not( target_feature = "sse2" ) ) ) {
6868 self . as_array( ) . iter( ) . sum( )
@@ -72,9 +72,9 @@ macro_rules! impl_float_reductions {
7272 }
7373 }
7474
75- /// Horizontal multiply. Returns the product of the lanes of the vector.
75+ /// Reducing multiply. Returns the product of the lanes of the vector.
7676 #[ inline]
77- pub fn horizontal_product ( self ) -> $scalar {
77+ pub fn reduce_product ( self ) -> $scalar {
7878 // LLVM product is inaccurate on i586
7979 if cfg!( all( target_arch = "x86" , not( target_feature = "sse2" ) ) ) {
8080 self . as_array( ) . iter( ) . product( )
@@ -84,22 +84,22 @@ macro_rules! impl_float_reductions {
8484 }
8585 }
8686
87- /// Horizontal maximum. Returns the maximum lane in the vector.
87+ /// Reducing maximum. Returns the maximum lane in the vector.
8888 ///
8989 /// Returns values based on equality, so a vector containing both `0.` and `-0.` may
9090 /// return either. This function will not return `NaN` unless all lanes are `NaN`.
9191 #[ inline]
92- pub fn horizontal_max ( self ) -> $scalar {
92+ pub fn reduce_max ( self ) -> $scalar {
9393 // Safety: `self` is a float vector
9494 unsafe { simd_reduce_max( self ) }
9595 }
9696
97- /// Horizontal minimum. Returns the minimum lane in the vector.
97+ /// Reducing minimum. Returns the minimum lane in the vector.
9898 ///
9999 /// Returns values based on equality, so a vector containing both `0.` and `-0.` may
100100 /// return either. This function will not return `NaN` unless all lanes are `NaN`.
101101 #[ inline]
102- pub fn horizontal_min ( self ) -> $scalar {
102+ pub fn reduce_min ( self ) -> $scalar {
103103 // Safety: `self` is a float vector
104104 unsafe { simd_reduce_min( self ) }
105105 }
@@ -116,10 +116,10 @@ where
116116 T : SimdElement + BitAnd < T , Output = T > ,
117117 LaneCount < LANES > : SupportedLaneCount ,
118118{
119- /// Horizontal bitwise "and". Returns the cumulative bitwise "and" across the lanes of
119+ /// Reducing bitwise "and". Returns the cumulative bitwise "and" across the lanes of
120120 /// the vector.
121121 #[ inline]
122- pub fn horizontal_and ( self ) -> T {
122+ pub fn reduce_and ( self ) -> T {
123123 unsafe { simd_reduce_and ( self ) }
124124 }
125125}
@@ -130,10 +130,10 @@ where
130130 T : SimdElement + BitOr < T , Output = T > ,
131131 LaneCount < LANES > : SupportedLaneCount ,
132132{
133- /// Horizontal bitwise "or". Returns the cumulative bitwise "or" across the lanes of
133+ /// Reducing bitwise "or". Returns the cumulative bitwise "or" across the lanes of
134134 /// the vector.
135135 #[ inline]
136- pub fn horizontal_or ( self ) -> T {
136+ pub fn reduce_or ( self ) -> T {
137137 unsafe { simd_reduce_or ( self ) }
138138 }
139139}
@@ -144,10 +144,10 @@ where
144144 T : SimdElement + BitXor < T , Output = T > ,
145145 LaneCount < LANES > : SupportedLaneCount ,
146146{
147- /// Horizontal bitwise "xor". Returns the cumulative bitwise "xor" across the lanes of
147+ /// Reducing bitwise "xor". Returns the cumulative bitwise "xor" across the lanes of
148148 /// the vector.
149149 #[ inline]
150- pub fn horizontal_xor ( self ) -> T {
150+ pub fn reduce_xor ( self ) -> T {
151151 unsafe { simd_reduce_xor ( self ) }
152152 }
153153}
0 commit comments