Try disabling div intrinsic on RISC-V

Author: calebzulawski

crates/core_simd/src/ops.rs

@@ -99,7 +99,7 @@ macro_rules! int_divrem_guard {
 
             // aarch64 div fails for arbitrary `v % 0`, mod fails when rhs is MIN, for non-powers-of-two
             // these operations aren't vectorized on aarch64 anyway
-            #[cfg(target_arch = "aarch64")]
+            #[cfg(any(target_arch = "aarch64", target_arch = "riscv32", target_arch = "riscv64"))]
             {
                 let mut out = Simd::splat(0 as _);
                 for i in 0..Self::LEN {
@@ -108,7 +108,7 @@ macro_rules! int_divrem_guard {
                 out
             }
 
-            #[cfg(not(target_arch = "aarch64"))]
+            #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv32", target_arch = "riscv64")))]
             {
                 // Safety: $lhs and rhs are vectors
                 unsafe { core::intrinsics::simd::$simd_call($lhs, rhs) }