Implement SimdFloat for f16

Author: sayantn

README.md

@@ -44,7 +44,7 @@ Currently, vectors may have up to 64 elements, but aliases are provided only up
 Depending on the size of the primitive type, the number of lanes the vector will have varies. For example, 128-bit vectors have four `f32` lanes and two `f64` lanes.
 
 The supported element types are as follows:
-* **Floating Point:** `f32`, `f64`
+* **Floating Point:** `f16`, `f32`, `f64`
 * **Signed Integers:** `i8`, `i16`, `i32`, `i64`, `isize` (`i128` excluded)
 * **Unsigned Integers:** `u8`, `u16`, `u32`, `u64`, `usize` (`u128` excluded)
 * **Pointers:** `*const T` and `*mut T` (zero-sized metadata only)

crates/core_simd/src/alias.rs

@@ -153,6 +153,16 @@ alias! {
         usizex64 64
     }
 
+    f16 = {
+        f16x1 1
+        f16x2 2
+        f16x4 4
+        f16x8 8
+        f16x16 16
+        f16x32 32
+        f16x64 64
+    }
+
     f32 = {
         f32x1 1
         f32x2 2

crates/core_simd/src/cast.rs

@@ -44,6 +44,9 @@ impl SimdCast for u64 {}
 unsafe impl Sealed for usize {}
 impl SimdCast for usize {}
 // Safety: primitive number types can be cast to other primitive number types
+unsafe impl Sealed for f16 {}
+impl SimdCast for f16 {}
+// Safety: primitive number types can be cast to other primitive number types
 unsafe impl Sealed for f32 {}
 impl SimdCast for f32 {}
 // Safety: primitive number types can be cast to other primitive number types

crates/core_simd/src/iter.rs

@@ -40,6 +40,7 @@ macro_rules! impl_traits {
     }
 }
 
+impl_traits! { f16 }
 impl_traits! { f32 }
 impl_traits! { f64 }
 impl_traits! { u8 }

crates/core_simd/src/lib.rs

@@ -10,7 +10,8 @@
     staged_api,
     prelude_import,
     ptr_metadata,
-    rustc_attrs
+    rustc_attrs,
+    f16
 )]
 #![cfg_attr(
     all(
@@ -35,6 +36,18 @@
     all(target_arch = "x86_64", target_feature = "avx512f"),
     feature(stdarch_x86_avx512)
 )]
+#![cfg_attr(
+    any(target_arch = "x86", target_arch = "x86_64"),
+    feature(stdarch_x86_avx512_f16)
+)]
+#![cfg_attr(
+    any(
+        target_arch = "aarch64",
+        target_arch = "arm64ec",
+        all(target_arch = "arm", target_feature = "v7"),
+    ),
+    feature(stdarch_neon_f16)
+)]
 #![warn(missing_docs, clippy::missing_inline_in_public_items)] // basically all items, really
 #![deny(
     unsafe_op_in_unsafe_fn,

crates/core_simd/src/ops.rs

@@ -245,7 +245,7 @@ for_base_ops! {
 // We don't need any special precautions here:
 // Floats always accept arithmetic ops, but may become NaN.
 for_base_ops! {
-    T = (f32, f64);
+    T = (f16, f32, f64);
     type Lhs = Simd<T, N>;
     type Rhs = Simd<T, N>;
     type Output = Self;

crates/core_simd/src/ops/unary.rs

@@ -19,6 +19,8 @@ macro_rules! neg {
 }
 
 neg! {
+    impl<const N: usize> Neg for Simd<f16, N>
+
     impl<const N: usize> Neg for Simd<f32, N>
 
     impl<const N: usize> Neg for Simd<f64, N>

crates/core_simd/src/simd/cmp/eq.rs

@@ -42,7 +42,7 @@ macro_rules! impl_number {
     }
 }
 
-impl_number! { f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize }
+impl_number! { f16, f32, f64, u8, u16, u32, u64, usize, i8, i16, i32, i64, isize }
 
 macro_rules! impl_mask {
     { $($integer:ty),* } => {

crates/core_simd/src/simd/cmp/ord.rs

@@ -144,7 +144,7 @@ macro_rules! impl_float {
     }
 }
 
-impl_float! { f32, f64 }
+impl_float! { f16, f32, f64 }
 
 macro_rules! impl_mask {
     { $($integer:ty),* } => {

crates/core_simd/src/simd/num/float.rs

@@ -444,4 +444,4 @@ macro_rules! impl_trait {
     }
 }
 
-impl_trait! { f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } }
+impl_trait! { f16 { bits: u16, mask: i16}, f32 { bits: u32, mask: i32 }, f64 { bits: u64, mask: i64 } }