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42 | 42 | //! order exists in which all threads observe all modifications in the same |
43 | 43 | //! order (see Sequentially-consistent ordering below) " |
44 | 44 | //! So in the absence of weak memory effects a seq-cst load & a seq-cst store is identical |
45 | | -//! to a acquire load and a release store given the global sequentially consistent order |
| 45 | +//! to an acquire load and a release store given the global sequentially consistent order |
46 | 46 | //! of the schedule. |
47 | 47 | //! |
48 | 48 | //! The timestamps used in the data-race detector assign each sequence of non-atomic operations |
@@ -142,7 +142,7 @@ impl ThreadClockSet { |
142 | 142 | self.fence_release.clone_from(&self.clock); |
143 | 143 | } |
144 | 144 |
|
145 | | - /// Apply the effects of a acquire fence to this |
| 145 | + /// Apply the effects of an acquire fence to this |
146 | 146 | /// set of thread vector clocks. |
147 | 147 | #[inline] |
148 | 148 | fn apply_acquire_fence(&mut self) { |
@@ -503,7 +503,7 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: MiriEvalContextExt<'mir, 'tcx> { |
503 | 503 | this.validate_atomic_store(dest, atomic) |
504 | 504 | } |
505 | 505 |
|
506 | | - /// Perform a atomic operation on a memory location. |
| 506 | + /// Perform an atomic operation on a memory location. |
507 | 507 | fn atomic_op_immediate( |
508 | 508 | &mut self, |
509 | 509 | place: &MPlaceTy<'tcx, Tag>, |
@@ -695,7 +695,7 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: MiriEvalContextExt<'mir, 'tcx> { |
695 | 695 | log::trace!("Atomic fence on {:?} with ordering {:?}", index, atomic); |
696 | 696 |
|
697 | 697 | // Apply data-race detection for the current fences |
698 | | - // this treats AcqRel and SeqCst as the same as a acquire |
| 698 | + // this treats AcqRel and SeqCst as the same as an acquire |
699 | 699 | // and release fence applied in the same timestamp. |
700 | 700 | if atomic != AtomicFenceOp::Release { |
701 | 701 | // Either Acquire | AcqRel | SeqCst |
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