Add support for BPF inline assembly

alessandrod · alessandrod · commit b2a6967114b2 · 2021-05-23T18:03:27.000+10:00
diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs
@@ -288,6 +288,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
                 InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
                 InlineAsmArch::SpirV => {}
                 InlineAsmArch::Wasm32 => {}
+                InlineAsmArch::Bpf => {}
             }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
@@ -593,6 +594,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
             InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
             InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
             InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
+            InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
+            InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
             InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
                 bug!("LLVM backend does not support SPIR-V")
             }
@@ -661,6 +664,7 @@ fn modifier_to_llvm(
         },
         InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
         InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None,
+        InlineAsmRegClass::Bpf(_) => None,
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
@@ -708,6 +712,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
         | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
         InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
         InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
+        InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
+        InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs
@@ -210,6 +210,8 @@ const WASM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
     ("nontrapping-fptoint", Some(sym::wasm_target_feature)),
 ];
 
+const BPF_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[("alu32", Some(sym::bpf_target_feature))];
+
 /// When rustdoc is running, provide a list of all known features so that all their respective
 /// primitives may be documented.
 ///
@@ -224,6 +226,7 @@ pub fn all_known_features() -> impl Iterator<Item = (&'static str, Option<Symbol
         .chain(MIPS_ALLOWED_FEATURES.iter())
         .chain(RISCV_ALLOWED_FEATURES.iter())
         .chain(WASM_ALLOWED_FEATURES.iter())
+        .chain(BPF_ALLOWED_FEATURES.iter())
         .cloned()
 }
 
@@ -237,6 +240,7 @@ pub fn supported_target_features(sess: &Session) -> &'static [(&'static str, Opt
         "powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES,
         "riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES,
         "wasm32" | "wasm64" => WASM_ALLOWED_FEATURES,
+        "bpf" => BPF_ALLOWED_FEATURES,
         _ => &[],
     }
 }
diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs
@@ -328,6 +328,7 @@ symbols! {
         box_free,
         box_patterns,
         box_syntax,
+        bpf_target_feature,
         braced_empty_structs,
         branch,
         breakpoint,
@@ -1332,6 +1333,7 @@ symbols! {
         wrapping_add,
         wrapping_mul,
         wrapping_sub,
+        wreg,
         write_bytes,
         xmm_reg,
         ymm_reg,
diff --git a/compiler/rustc_target/src/abi/call/mod.rs b/compiler/rustc_target/src/abi/call/mod.rs
@@ -655,7 +655,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
                 }
             }
             "asmjs" => wasm::compute_c_abi_info(cx, self),
-            "bpfel" | "bpfeb" => bpf::compute_abi_info(self),
+            "bpf" => bpf::compute_abi_info(self),
             a => return Err(format!("unrecognized arch \"{}\" in target specification", a)),
         }
 
diff --git a/compiler/rustc_target/src/asm/bpf.rs b/compiler/rustc_target/src/asm/bpf.rs
@@ -0,0 +1,129 @@
+use super::{InlineAsmArch, InlineAsmType, Target};
+use rustc_macros::HashStable_Generic;
+use std::fmt;
+
+def_reg_class! {
+    Bpf BpfInlineAsmRegClass {
+        reg,
+        wreg,
+    }
+}
+
+impl BpfInlineAsmRegClass {
+    pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
+        &[]
+    }
+
+    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
+        None
+    }
+
+    pub fn suggest_modifier(
+        self,
+        _arch: InlineAsmArch,
+        _ty: InlineAsmType,
+    ) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn supported_types(
+        self,
+        _arch: InlineAsmArch,
+    ) -> &'static [(InlineAsmType, Option<&'static str>)] {
+        match self {
+            Self::reg => types! { _: I8, I16, I32, I64; },
+            Self::wreg => types! { "alu32": I8, I16, I32; },
+        }
+    }
+}
+
+fn only_alu32(
+    _arch: InlineAsmArch,
+    mut has_feature: impl FnMut(&str) -> bool,
+    _target: &Target,
+) -> Result<(), &'static str> {
+    if !has_feature("alu32") {
+        Err("register can't be used without the `alu32` target feature")
+    } else {
+        Ok(())
+    }
+}
+
+def_regs! {
+    Bpf BpfInlineAsmReg BpfInlineAsmRegClass {
+        r0: reg = ["r0"],
+        r1: reg = ["r1"],
+        r2: reg = ["r2"],
+        r3: reg = ["r3"],
+        r4: reg = ["r4"],
+        r5: reg = ["r5"],
+        r6: reg = ["r6"],
+        r7: reg = ["r7"],
+        r8: reg = ["r8"],
+        r9: reg = ["r9"],
+        w0: wreg = ["w0"] % only_alu32,
+        w1: wreg = ["w1"] % only_alu32,
+        w2: wreg = ["w2"] % only_alu32,
+        w3: wreg = ["w3"] % only_alu32,
+        w4: wreg = ["w4"] % only_alu32,
+        w5: wreg = ["w5"] % only_alu32,
+        w6: wreg = ["w6"] % only_alu32,
+        w7: wreg = ["w7"] % only_alu32,
+        w8: wreg = ["w8"] % only_alu32,
+        w9: wreg = ["w9"] % only_alu32,
+
+        #error = ["r10", "w10"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+    }
+}
+
+impl BpfInlineAsmReg {
+    pub fn emit(
+        self,
+        out: &mut dyn fmt::Write,
+        _arch: InlineAsmArch,
+        _modifier: Option<char>,
+    ) -> fmt::Result {
+        out.write_str(self.name())
+    }
+
+    pub fn overlapping_regs(self, mut cb: impl FnMut(BpfInlineAsmReg)) {
+        cb(self);
+
+        macro_rules! reg_conflicts {
+            (
+                $(
+                    $r:ident : $w:ident
+                ),*
+            ) => {
+                match self {
+                    $(
+                        Self::$r => {
+                            cb(Self::$w);
+                        }
+                        Self::$w => {
+                            cb(Self::$r);
+                        }
+                    )*
+                }
+            };
+        }
+
+        reg_conflicts! {
+            r0 : w0,
+            r1 : w1,
+            r2 : w2,
+            r3 : w3,
+            r4 : w4,
+            r5 : w5,
+            r6 : w6,
+            r7 : w7,
+            r8 : w8,
+            r9 : w9
+        }
+    }
+}
diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs
@@ -148,6 +148,7 @@ macro_rules! types {
 
 mod aarch64;
 mod arm;
+mod bpf;
 mod hexagon;
 mod mips;
 mod nvptx;
@@ -159,6 +160,7 @@ mod x86;
 
 pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
 pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
+pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass};
 pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
 pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
 pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
@@ -184,6 +186,7 @@ pub enum InlineAsmArch {
     PowerPC64,
     SpirV,
     Wasm32,
+    Bpf,
 }
 
 impl FromStr for InlineAsmArch {
@@ -205,6 +208,7 @@ impl FromStr for InlineAsmArch {
             "mips64" => Ok(Self::Mips64),
             "spirv" => Ok(Self::SpirV),
             "wasm32" => Ok(Self::Wasm32),
+            "bpf" => Ok(Self::Bpf),
             _ => Err(()),
         }
     }
@@ -233,6 +237,7 @@ pub enum InlineAsmReg {
     Mips(MipsInlineAsmReg),
     SpirV(SpirVInlineAsmReg),
     Wasm(WasmInlineAsmReg),
+    Bpf(BpfInlineAsmReg),
     // Placeholder for invalid register constraints for the current target
     Err,
 }
@@ -247,6 +252,7 @@ impl InlineAsmReg {
             Self::PowerPC(r) => r.name(),
             Self::Hexagon(r) => r.name(),
             Self::Mips(r) => r.name(),
+            Self::Bpf(r) => r.name(),
             Self::Err => "<reg>",
         }
     }
@@ -260,6 +266,7 @@ impl InlineAsmReg {
             Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),
             Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
             Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
+            Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
             Self::Err => InlineAsmRegClass::Err,
         }
     }
@@ -304,6 +311,9 @@ impl InlineAsmReg {
             InlineAsmArch::Wasm32 => {
                 Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, &name)?)
             }
+            InlineAsmArch::Bpf => {
+                Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)
+            }
         })
     }
 
@@ -323,6 +333,7 @@ impl InlineAsmReg {
             Self::PowerPC(r) => r.emit(out, arch, modifier),
             Self::Hexagon(r) => r.emit(out, arch, modifier),
             Self::Mips(r) => r.emit(out, arch, modifier),
+            Self::Bpf(r) => r.emit(out, arch, modifier),
             Self::Err => unreachable!("Use of InlineAsmReg::Err"),
         }
     }
@@ -336,6 +347,7 @@ impl InlineAsmReg {
             Self::PowerPC(_) => cb(self),
             Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
             Self::Mips(_) => cb(self),
+            Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
             Self::Err => unreachable!("Use of InlineAsmReg::Err"),
         }
     }
@@ -364,6 +376,7 @@ pub enum InlineAsmRegClass {
     Mips(MipsInlineAsmRegClass),
     SpirV(SpirVInlineAsmRegClass),
     Wasm(WasmInlineAsmRegClass),
+    Bpf(BpfInlineAsmRegClass),
     // Placeholder for invalid register constraints for the current target
     Err,
 }
@@ -381,6 +394,7 @@ impl InlineAsmRegClass {
             Self::Mips(r) => r.name(),
             Self::SpirV(r) => r.name(),
             Self::Wasm(r) => r.name(),
+            Self::Bpf(r) => r.name(),
             Self::Err => rustc_span::symbol::sym::reg,
         }
     }
@@ -400,6 +414,7 @@ impl InlineAsmRegClass {
             Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
             Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
             Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
+            Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -426,6 +441,7 @@ impl InlineAsmRegClass {
             Self::Mips(r) => r.suggest_modifier(arch, ty),
             Self::SpirV(r) => r.suggest_modifier(arch, ty),
             Self::Wasm(r) => r.suggest_modifier(arch, ty),
+            Self::Bpf(r) => r.suggest_modifier(arch, ty),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -448,6 +464,7 @@ impl InlineAsmRegClass {
             Self::Mips(r) => r.default_modifier(arch),
             Self::SpirV(r) => r.default_modifier(arch),
             Self::Wasm(r) => r.default_modifier(arch),
+            Self::Bpf(r) => r.default_modifier(arch),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -469,6 +486,7 @@ impl InlineAsmRegClass {
             Self::Mips(r) => r.supported_types(arch),
             Self::SpirV(r) => r.supported_types(arch),
             Self::Wasm(r) => r.supported_types(arch),
+            Self::Bpf(r) => r.supported_types(arch),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -493,6 +511,7 @@ impl InlineAsmRegClass {
             }
             InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
             InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?),
+            InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
         })
     }
 
@@ -510,6 +529,7 @@ impl InlineAsmRegClass {
             Self::Mips(r) => r.valid_modifiers(arch),
             Self::SpirV(r) => r.valid_modifiers(arch),
             Self::Wasm(r) => r.valid_modifiers(arch),
+            Self::Bpf(r) => r.valid_modifiers(arch),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -679,5 +699,10 @@ pub fn allocatable_registers(
             wasm::fill_reg_map(arch, has_feature, target, &mut map);
             map
         }
+        InlineAsmArch::Bpf => {
+            let mut map = bpf::regclass_map();
+            bpf::fill_reg_map(arch, has_feature, target, &mut map);
+            map
+        }
     }
 }
diff --git a/compiler/rustc_target/src/spec/bpf_base.rs b/compiler/rustc_target/src/spec/bpf_base.rs
@@ -3,6 +3,7 @@ use crate::{abi::Endian, spec::abi::Abi};
 
 pub fn opts(endian: Endian) -> TargetOptions {
     TargetOptions {
+        allow_asm: true,
         endian,
         linker_flavor: LinkerFlavor::BpfLinker,
         atomic_cas: false,
diff --git a/compiler/rustc_target/src/spec/bpfeb_unknown_none.rs b/compiler/rustc_target/src/spec/bpfeb_unknown_none.rs
@@ -6,7 +6,7 @@ pub fn target() -> Target {
         llvm_target: "bpfeb".to_string(),
         data_layout: "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128".to_string(),
         pointer_width: 64,
-        arch: "bpfeb".to_string(),
+        arch: "bpf".to_string(),
         options: bpf_base::opts(Endian::Big),
     }
 }
diff --git a/compiler/rustc_target/src/spec/bpfel_unknown_none.rs b/compiler/rustc_target/src/spec/bpfel_unknown_none.rs
@@ -6,7 +6,7 @@ pub fn target() -> Target {
         llvm_target: "bpfel".to_string(),
         data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".to_string(),
         pointer_width: 64,
-        arch: "bpfel".to_string(),
+        arch: "bpf".to_string(),
         options: bpf_base::opts(Endian::Little),
     }
 }
diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md

Original file line number	Diff line number	Diff line change
`@@ -655,7 +655,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {`
`655`	`655`	`}`
`656`	`656`	`}`
`657`	`657`	`"asmjs" => wasm::compute_c_abi_info(cx, self),`
`658`		`- "bpfel" \| "bpfeb" => bpf::compute_abi_info(self),`
	`658`	`+ "bpf" => bpf::compute_abi_info(self),`
`659`	`659`	`a => return Err(format!("unrecognized arch \"{}\" in target specification", a)),`
`660`	`660`	`}`
`661`	`661`
Original file line number	Diff line number	Diff line change
`@@ -148,6 +148,7 @@ macro_rules! types {`
`148`	`148`
`149`	`149`	`mod aarch64;`
`150`	`150`	`mod arm;`
	`151`	`+mod bpf;`
`151`	`152`	`mod hexagon;`
`152`	`153`	`mod mips;`
`153`	`154`	`mod nvptx;`
`@@ -159,6 +160,7 @@ mod x86;`
`159`	`160`
`160`	`161`	`pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};`
`161`	`162`	`pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};`
	`163`	`+pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass};`
`162`	`164`	`pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};`
`163`	`165`	`pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};`
`164`	`166`	`pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};`
`@@ -184,6 +186,7 @@ pub enum InlineAsmArch {`
`184`	`186`	`PowerPC64,`
`185`	`187`	`SpirV,`
`186`	`188`	`Wasm32,`
	`189`	`+ Bpf,`
`187`	`190`	`}`
`188`	`191`
`189`	`192`	`impl FromStr for InlineAsmArch {`
`@@ -205,6 +208,7 @@ impl FromStr for InlineAsmArch {`
`205`	`208`	`"mips64" => Ok(Self::Mips64),`
`206`	`209`	`"spirv" => Ok(Self::SpirV),`
`207`	`210`	`"wasm32" => Ok(Self::Wasm32),`
	`211`	`+ "bpf" => Ok(Self::Bpf),`
`208`	`212`	`_ => Err(()),`
`209`	`213`	`}`
`210`	`214`	`}`
`@@ -233,6 +237,7 @@ pub enum InlineAsmReg {`
`233`	`237`	`Mips(MipsInlineAsmReg),`
`234`	`238`	`SpirV(SpirVInlineAsmReg),`
`235`	`239`	`Wasm(WasmInlineAsmReg),`
	`240`	`+ Bpf(BpfInlineAsmReg),`
`236`	`241`	`// Placeholder for invalid register constraints for the current target`
`237`	`242`	`Err,`
`238`	`243`	`}`
`@@ -247,6 +252,7 @@ impl InlineAsmReg {`
`247`	`252`	`Self::PowerPC(r) => r.name(),`
`248`	`253`	`Self::Hexagon(r) => r.name(),`
`249`	`254`	`Self::Mips(r) => r.name(),`
	`255`	`+ Self::Bpf(r) => r.name(),`
`250`	`256`	`Self::Err => "<reg>",`
`251`	`257`	`}`
`252`	`258`	`}`
`@@ -260,6 +266,7 @@ impl InlineAsmReg {`
`260`	`266`	`Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),`
`261`	`267`	`Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),`
`262`	`268`	`Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),`
	`269`	`+ Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),`
`263`	`270`	`Self::Err => InlineAsmRegClass::Err,`
`264`	`271`	`}`
`265`	`272`	`}`
`@@ -304,6 +311,9 @@ impl InlineAsmReg {`
`304`	`311`	`InlineAsmArch::Wasm32 => {`
`305`	`312`	`Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, &name)?)`
`306`	`313`	`}`
	`314`	`+ InlineAsmArch::Bpf => {`
	`315`	`+ Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)`
	`316`	`+ }`
`307`	`317`	`})`
`308`	`318`	`}`
`309`	`319`
`@@ -323,6 +333,7 @@ impl InlineAsmReg {`
`323`	`333`	`Self::PowerPC(r) => r.emit(out, arch, modifier),`
`324`	`334`	`Self::Hexagon(r) => r.emit(out, arch, modifier),`
`325`	`335`	`Self::Mips(r) => r.emit(out, arch, modifier),`
	`336`	`+ Self::Bpf(r) => r.emit(out, arch, modifier),`
`326`	`337`	`Self::Err => unreachable!("Use of InlineAsmReg::Err"),`
`327`	`338`	`}`
`328`	`339`	`}`
`@@ -336,6 +347,7 @@ impl InlineAsmReg {`
`336`	`347`	`Self::PowerPC(_) => cb(self),`
`337`	`348`	`Self::Hexagon(r) => r.overlapping_regs(\|r\| cb(Self::Hexagon(r))),`
`338`	`349`	`Self::Mips(_) => cb(self),`
	`350`	`+ Self::Bpf(r) => r.overlapping_regs(\|r\| cb(Self::Bpf(r))),`
`339`	`351`	`Self::Err => unreachable!("Use of InlineAsmReg::Err"),`
`340`	`352`	`}`
`341`	`353`	`}`
`@@ -364,6 +376,7 @@ pub enum InlineAsmRegClass {`
`364`	`376`	`Mips(MipsInlineAsmRegClass),`
`365`	`377`	`SpirV(SpirVInlineAsmRegClass),`
`366`	`378`	`Wasm(WasmInlineAsmRegClass),`
	`379`	`+ Bpf(BpfInlineAsmRegClass),`
`367`	`380`	`// Placeholder for invalid register constraints for the current target`
`368`	`381`	`Err,`
`369`	`382`	`}`
`@@ -381,6 +394,7 @@ impl InlineAsmRegClass {`
`381`	`394`	`Self::Mips(r) => r.name(),`
`382`	`395`	`Self::SpirV(r) => r.name(),`
`383`	`396`	`Self::Wasm(r) => r.name(),`
	`397`	`+ Self::Bpf(r) => r.name(),`
`384`	`398`	`Self::Err => rustc_span::symbol::sym::reg,`
`385`	`399`	`}`
`386`	`400`	`}`
`@@ -400,6 +414,7 @@ impl InlineAsmRegClass {`
`400`	`414`	`Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),`
`401`	`415`	`Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),`
`402`	`416`	`Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),`
	`417`	`+ Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),`
`403`	`418`	`Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),`
`404`	`419`	`}`
`405`	`420`	`}`
`@@ -426,6 +441,7 @@ impl InlineAsmRegClass {`
`426`	`441`	`Self::Mips(r) => r.suggest_modifier(arch, ty),`
`427`	`442`	`Self::SpirV(r) => r.suggest_modifier(arch, ty),`
`428`	`443`	`Self::Wasm(r) => r.suggest_modifier(arch, ty),`
	`444`	`+ Self::Bpf(r) => r.suggest_modifier(arch, ty),`
`429`	`445`	`Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),`
`430`	`446`	`}`
`431`	`447`	`}`
`@@ -448,6 +464,7 @@ impl InlineAsmRegClass {`
`448`	`464`	`Self::Mips(r) => r.default_modifier(arch),`
`449`	`465`	`Self::SpirV(r) => r.default_modifier(arch),`
`450`	`466`	`Self::Wasm(r) => r.default_modifier(arch),`
	`467`	`+ Self::Bpf(r) => r.default_modifier(arch),`
`451`	`468`	`Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),`
`452`	`469`	`}`
`453`	`470`	`}`
`@@ -469,6 +486,7 @@ impl InlineAsmRegClass {`
`469`	`486`	`Self::Mips(r) => r.supported_types(arch),`
`470`	`487`	`Self::SpirV(r) => r.supported_types(arch),`
`471`	`488`	`Self::Wasm(r) => r.supported_types(arch),`
	`489`	`+ Self::Bpf(r) => r.supported_types(arch),`
`472`	`490`	`Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),`
`473`	`491`	`}`
`474`	`492`	`}`
`@@ -493,6 +511,7 @@ impl InlineAsmRegClass {`
`493`	`511`	`}`
`494`	`512`	`InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),`
`495`	`513`	`InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?),`
	`514`	`+ InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),`
`496`	`515`	`})`
`497`	`516`	`}`
`498`	`517`
`@@ -510,6 +529,7 @@ impl InlineAsmRegClass {`
`510`	`529`	`Self::Mips(r) => r.valid_modifiers(arch),`
`511`	`530`	`Self::SpirV(r) => r.valid_modifiers(arch),`
`512`	`531`	`Self::Wasm(r) => r.valid_modifiers(arch),`
	`532`	`+ Self::Bpf(r) => r.valid_modifiers(arch),`
`513`	`533`	`Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),`
`514`	`534`	`}`
`515`	`535`	`}`
`@@ -679,5 +699,10 @@ pub fn allocatable_registers(`
`679`	`699`	`wasm::fill_reg_map(arch, has_feature, target, &mut map);`
`680`	`700`	`map`
`681`	`701`	`}`
	`702`	`+ InlineAsmArch::Bpf => {`
	`703`	`+ let mut map = bpf::regclass_map();`
	`704`	`+ bpf::fill_reg_map(arch, has_feature, target, &mut map);`
	`705`	`+ map`
	`706`	`+ }`
`682`	`707`	`}`
`683`	`708`	`}`
Original file line number	Diff line number	Diff line change
`@@ -6,7 +6,7 @@ pub fn target() -> Target {`
`6`	`6`	`llvm_target: "bpfeb".to_string(),`
`7`	`7`	`data_layout: "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128".to_string(),`
`8`	`8`	`pointer_width: 64,`
`9`		`- arch: "bpfeb".to_string(),`
	`9`	`+ arch: "bpf".to_string(),`
`10`	`10`	`options: bpf_base::opts(Endian::Big),`
`11`	`11`	`}`
`12`	`12`	`}`
Original file line number	Diff line number	Diff line change
`@@ -6,7 +6,7 @@ pub fn target() -> Target {`
`6`	`6`	`llvm_target: "bpfel".to_string(),`
`7`	`7`	`data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".to_string(),`
`8`	`8`	`pointer_width: 64,`
`9`		`- arch: "bpfel".to_string(),`
	`9`	`+ arch: "bpf".to_string(),`
`10`	`10`	`options: bpf_base::opts(Endian::Little),`
`11`	`11`	`}`
`12`	`12`	`}`