@@ -2,7 +2,8 @@ use crate::simd::intrinsics::{
22 simd_reduce_add_ordered, simd_reduce_and, simd_reduce_max, simd_reduce_min,
33 simd_reduce_mul_ordered, simd_reduce_or, simd_reduce_xor,
44} ;
5- use crate :: simd:: { LaneCount , Simd , SupportedLaneCount } ;
5+ use crate :: simd:: { LaneCount , Simd , SimdElement , SupportedLaneCount } ;
6+ use core:: ops:: { BitAnd , BitOr , BitXor } ;
67
78macro_rules! impl_integer_reductions {
89 { $scalar: ty } => {
@@ -22,27 +23,6 @@ macro_rules! impl_integer_reductions {
2223 unsafe { simd_reduce_mul_ordered( self , 1 ) }
2324 }
2425
25- /// Horizontal bitwise "and". Returns the cumulative bitwise "and" across the lanes of
26- /// the vector.
27- #[ inline]
28- pub fn horizontal_and( self ) -> $scalar {
29- unsafe { simd_reduce_and( self ) }
30- }
31-
32- /// Horizontal bitwise "or". Returns the cumulative bitwise "or" across the lanes of
33- /// the vector.
34- #[ inline]
35- pub fn horizontal_or( self ) -> $scalar {
36- unsafe { simd_reduce_or( self ) }
37- }
38-
39- /// Horizontal bitwise "xor". Returns the cumulative bitwise "xor" across the lanes of
40- /// the vector.
41- #[ inline]
42- pub fn horizontal_xor( self ) -> $scalar {
43- unsafe { simd_reduce_xor( self ) }
44- }
45-
4626 /// Horizontal maximum. Returns the maximum lane in the vector.
4727 #[ inline]
4828 pub fn horizontal_max( self ) -> $scalar {
@@ -121,3 +101,45 @@ macro_rules! impl_float_reductions {
121101
122102impl_float_reductions ! { f32 }
123103impl_float_reductions ! { f64 }
104+
105+ impl < T , const LANES : usize > Simd < T , LANES >
106+ where
107+ Self : BitAnd < Self , Output = Self > ,
108+ T : SimdElement + BitAnd < T , Output = T > ,
109+ LaneCount < LANES > : SupportedLaneCount ,
110+ {
111+ /// Horizontal bitwise "and". Returns the cumulative bitwise "and" across the lanes of
112+ /// the vector.
113+ #[ inline]
114+ pub fn horizontal_and ( self ) -> T {
115+ unsafe { simd_reduce_and ( self ) }
116+ }
117+ }
118+
119+ impl < T , const LANES : usize > Simd < T , LANES >
120+ where
121+ Self : BitOr < Self , Output = Self > ,
122+ T : SimdElement + BitOr < T , Output = T > ,
123+ LaneCount < LANES > : SupportedLaneCount ,
124+ {
125+ /// Horizontal bitwise "or". Returns the cumulative bitwise "or" across the lanes of
126+ /// the vector.
127+ #[ inline]
128+ pub fn horizontal_or ( self ) -> T {
129+ unsafe { simd_reduce_or ( self ) }
130+ }
131+ }
132+
133+ impl < T , const LANES : usize > Simd < T , LANES >
134+ where
135+ Self : BitXor < Self , Output = Self > ,
136+ T : SimdElement + BitXor < T , Output = T > ,
137+ LaneCount < LANES > : SupportedLaneCount ,
138+ {
139+ /// Horizontal bitwise "xor". Returns the cumulative bitwise "xor" across the lanes of
140+ /// the vector.
141+ #[ inline]
142+ pub fn horizontal_xor ( self ) -> T {
143+ unsafe { simd_reduce_xor ( self ) }
144+ }
145+ }
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