@@ -893,36 +893,6 @@ trait EvalContextExtPriv<'mir, 'tcx: 'mir>: crate::MiriInterpCxExt<'mir, 'tcx> {
893893 throw_unsup_format ! ( "unsupported `llvm.prefetch` type argument: {}" , ty) ;
894894 }
895895 }
896- // FIXME: Move these to an `arm` submodule.
897- "llvm.aarch64.isb" if this. tcx . sess . target . arch == "aarch64" => {
898- let [ arg] = this. check_shim ( abi, Abi :: Unadjusted , link_name, args) ?;
899- let arg = this. read_scalar ( arg) ?. to_i32 ( ) ?;
900- match arg {
901- // SY ("full system scope")
902- 15 => {
903- this. yield_active_thread ( ) ;
904- }
905- _ => {
906- throw_unsup_format ! ( "unsupported llvm.aarch64.isb argument {}" , arg) ;
907- }
908- }
909- }
910- "llvm.arm.hint" if this. tcx . sess . target . arch == "arm" => {
911- let [ arg] = this. check_shim ( abi, Abi :: Unadjusted , link_name, args) ?;
912- let arg = this. read_scalar ( arg) ?. to_i32 ( ) ?;
913- // Note that different arguments might have different target feature requirements.
914- match arg {
915- // YIELD
916- 1 => {
917- this. expect_target_feature_for_intrinsic ( link_name, "v6" ) ?;
918- this. yield_active_thread ( ) ;
919- }
920- _ => {
921- throw_unsup_format ! ( "unsupported llvm.arm.hint argument {}" , arg) ;
922- }
923- }
924- }
925-
926896 // Used to implement the x86 `_mm{,256,512}_popcnt_epi{8,16,32,64}` and wasm
927897 // `{i,u}8x16_popcnt` functions.
928898 name if name. starts_with ( "llvm.ctpop.v" ) => {
@@ -946,6 +916,7 @@ trait EvalContextExtPriv<'mir, 'tcx: 'mir>: crate::MiriInterpCxExt<'mir, 'tcx> {
946916 }
947917 }
948918
919+ // Target-specific shims
949920 name if name. starts_with ( "llvm.x86." )
950921 && ( this. tcx . sess . target . arch == "x86"
951922 || this. tcx . sess . target . arch == "x86_64" ) =>
@@ -954,6 +925,35 @@ trait EvalContextExtPriv<'mir, 'tcx: 'mir>: crate::MiriInterpCxExt<'mir, 'tcx> {
954925 this, link_name, abi, args, dest,
955926 ) ;
956927 }
928+ // FIXME: Move these to an `arm` submodule.
929+ "llvm.aarch64.isb" if this. tcx . sess . target . arch == "aarch64" => {
930+ let [ arg] = this. check_shim ( abi, Abi :: Unadjusted , link_name, args) ?;
931+ let arg = this. read_scalar ( arg) ?. to_i32 ( ) ?;
932+ match arg {
933+ // SY ("full system scope")
934+ 15 => {
935+ this. yield_active_thread ( ) ;
936+ }
937+ _ => {
938+ throw_unsup_format ! ( "unsupported llvm.aarch64.isb argument {}" , arg) ;
939+ }
940+ }
941+ }
942+ "llvm.arm.hint" if this. tcx . sess . target . arch == "arm" => {
943+ let [ arg] = this. check_shim ( abi, Abi :: Unadjusted , link_name, args) ?;
944+ let arg = this. read_scalar ( arg) ?. to_i32 ( ) ?;
945+ // Note that different arguments might have different target feature requirements.
946+ match arg {
947+ // YIELD
948+ 1 => {
949+ this. expect_target_feature_for_intrinsic ( link_name, "v6" ) ?;
950+ this. yield_active_thread ( ) ;
951+ }
952+ _ => {
953+ throw_unsup_format ! ( "unsupported llvm.arm.hint argument {}" , arg) ;
954+ }
955+ }
956+ }
957957
958958 // Platform-specific shims
959959 _ =>
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