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Commit 3954b74

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SergioGasquezSergioGasquez
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feat: Add std Xtensa targets support
1 parent f6b4b71 commit 3954b74

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8 files changed

+144
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‎compiler/rustc_target/src/spec/mod.rs‎

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@@ -1767,8 +1767,11 @@ supported_targets! {
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("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
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("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
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("xtensa-esp32-espidf", xtensa_esp32_espidf),
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("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
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("xtensa-esp32s2-espidf", xtensa_esp32s2_espidf),
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("xtensa-esp32s3-none-elf", xtensa_esp32s3_none_elf),
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("xtensa-esp32s3-espidf", xtensa_esp32s3_espidf),
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("i686-wrs-vxworks", i686_wrs_vxworks),
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("x86_64-wrs-vxworks", x86_64_wrs_vxworks),

‎compiler/rustc_target/src/spec/targets/xtensa_esp32_espidf.rs‎

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use crate::abi::Endian;
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use crate::spec::{base::xtensa, cvs, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "xtensa-none-elf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
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arch: "xtensa".into(),
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metadata: crate::spec::TargetMetadata {
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description: None,
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tier: None,
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host_tools: None,
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std: None,
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},
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options: TargetOptions {
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endian: Endian::Little,
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c_int_width: "32".into(),
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families: cvs!["unix"],
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os: "espidf".into(),
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env: "newlib".into(),
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vendor: "espressif".into(),
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executables: true,
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cpu: "esp32".into(),
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linker: Some("xtensa-esp32-elf-gcc".into()),
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// The esp32 only supports native 32bit atomics.
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max_atomic_width: Some(32),
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atomic_cas: true,
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..xtensa::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/xtensa_esp32s2_espidf.rs‎

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use crate::abi::Endian;
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use crate::spec::{base::xtensa, cvs, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "xtensa-none-elf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
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arch: "xtensa".into(),
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metadata: crate::spec::TargetMetadata {
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description: None,
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tier: None,
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host_tools: None,
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std: None,
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},
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options: TargetOptions {
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endian: Endian::Little,
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c_int_width: "32".into(),
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families: cvs!["unix"],
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os: "espidf".into(),
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env: "newlib".into(),
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vendor: "espressif".into(),
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executables: true,
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cpu: "esp32-s2".into(),
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linker: Some("xtensa-esp32s2-elf-gcc".into()),
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// See https://github.com/espressif/rust-esp32-example/issues/3#issuecomment-861054477
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//
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// While the ESP32-S2 chip does not natively support atomics, ESP-IDF does support
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// the __atomic* and __sync* compiler builtins. Setting `max_atomic_width` and `atomic_cas`
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// and `atomic_cas: true` will cause the compiler to emit libcalls to these builtins. On the
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// ESP32-S2, these are guaranteed to be lock-free.
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//
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// Support for atomics is necessary for the Rust STD library, which is supported by ESP-IDF.
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max_atomic_width: Some(32),
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atomic_cas: true,
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..xtensa::opts()
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},
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}
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}

‎compiler/rustc_target/src/spec/targets/xtensa_esp32s3_espidf.rs‎

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use crate::abi::Endian;
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use crate::spec::{base::xtensa, cvs, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "xtensa-none-elf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(),
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arch: "xtensa".into(),
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metadata: crate::spec::TargetMetadata {
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description: None,
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tier: None,
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host_tools: None,
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std: None,
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},
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options: TargetOptions {
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endian: Endian::Little,
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c_int_width: "32".into(),
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families: cvs!["unix"],
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os: "espidf".into(),
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env: "newlib".into(),
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vendor: "espressif".into(),
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executables: true,
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cpu: "esp32-s3".into(),
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linker: Some("xtensa-esp32s3-elf-gcc".into()),
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// The esp32s3 only supports native 32bit atomics.
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max_atomic_width: Some(32),
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atomic_cas: true,
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..xtensa::opts()
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},
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}
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}

‎src/doc/rustc/src/platform-support.md‎

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@@ -384,7 +384,10 @@ target | std | host | notes
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[`x86_64h-apple-darwin`](platform-support/x86_64h-apple-darwin.md) | ✓ | ✓ | macOS with late-gen Intel (at least Haswell)
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[`x86_64-unknown-linux-none`](platform-support/x86_64-unknown-linux-none.md) | * | | 64-bit Linux with no libc
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`xtensa-esp32-none-elf` | | | Xtensa ESP32
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`xtensa-esp32-espidf` | | | Xtensa ESP32
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`xtensa-esp32s2-none-elf` | | | Xtensa ESP32-S2
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`xtensa-esp32s2-espidf` | | | Xtensa ESP32-S2
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`xtensa-esp32s3-none-elf` | | | Xtensa ESP32-S3
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`xtensa-esp32s3-espidf` | | | Xtensa ESP32-S3
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[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets

‎src/doc/rustc/src/platform-support/xtensa.md‎

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@@ -13,13 +13,23 @@ Targets for Xtensa CPUs.
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The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined:
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### `no_std`
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| Target name | Target CPU(s) |
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| ------------------------- | --------------------------------------------------------------- |
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| `xtensa-esp32-none-elf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) |
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| `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
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| `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
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### `std`
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| Target name | Target CPU(s) |
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| ----------------------- | --------------------------------------------------------------- |
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| `xtensa-esp32-espidf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) |
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| `xtensa-esp32s2-espidf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) |
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| `xtensa-esp32s3-espidf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) |
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## Building the target
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## Building the targets
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The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of the The Rust on ESP Book](https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html).

‎src/tools/tidy/src/target_policy.rs‎

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@@ -14,8 +14,11 @@ const EXCEPTIONS: &[&str] = &[
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"csky_unknown_linux_gnuabiv2hf",
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// FIXME: disabled since it requires a custom LLVM until the upstream LLVM adds support for the target (https://github.com/espressif/llvm-project/issues/4)
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"xtensa_esp32_none_elf",
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"xtensa_esp32_espidf",
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"xtensa_esp32s2_none_elf",
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"xtensa_esp32s2_espidf",
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"xtensa_esp32s3_none_elf",
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"xtensa_esp32s3_espidf",
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];
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pub fn check(root_path: &Path, bad: &mut bool) {

‎tests/assembly/targets/targets-elf.rs‎

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revisions: xtensa_esp32_none_elf
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[xtensa_esp32_none_elf] compile-flags: --target xtensa-esp32-none-elf
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[xtensa_esp32_none_elf] needs-llvm-components: xtensa
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revisions: xtensa_esp32_espidf
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[xtensa_esp32_espidf] compile-flags: --target xtensa-esp32s2-espidf
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[xtensa_esp32_espidf] needs-llvm-components: xtensa
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revisions: xtensa_esp32s2_none_elf
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[xtensa_esp32s2_none_elf] compile-flags: --target xtensa-esp32s2-none-elf
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[xtensa_esp32s2_none_elf] needs-llvm-components: xtensa
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revisions: xtensa_esp32s2_espidf
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[xtensa_esp32s2_espidf] compile-flags: --target xtensa-esp32s2-espidf
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[xtensa_esp32s2_espidf] needs-llvm-components: xtensa
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revisions: xtensa_esp32s3_none_elf
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[xtensa_esp32s3_none_elf] compile-flags: --target xtensa-esp32s3-none-elf
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[xtensa_esp32s3_none_elf] needs-llvm-components: xtensa
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revisions: xtensa_esp32s3_espidf
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[xtensa_esp32s3_espidf] compile-flags: --target xtensa-esp32s3-espidf
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[xtensa_esp32s3_espidf] needs-llvm-components: xtensa
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*/
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// Sanity-check that each target can produce assembly code.
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