Change capitalization of Spirv to SpirV

khyperia · khyperia · commit 0e34b73996e8 · 2020-11-11T19:18:06.000+01:00
This matches the capitalization of RiscV
diff --git a/compiler/rustc_codegen_llvm/src/asm.rs b/compiler/rustc_codegen_llvm/src/asm.rs
@@ -260,7 +260,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
                 InlineAsmArch::Nvptx64 => {}
                 InlineAsmArch::Hexagon => {}
                 InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
-                InlineAsmArch::Spirv => {}
+                InlineAsmArch::SpirV => {}
             }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
@@ -519,7 +519,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
             | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",
             InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",
             InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",
-            InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
+            InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
                 bug!("LLVM backend does not support SPIR-V")
             }
         }
@@ -584,7 +584,7 @@ fn modifier_to_llvm(
             _ => unreachable!(),
         },
         InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,
-        InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
+        InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
     }
@@ -626,7 +626,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
         | InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
         | InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),
         InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),
-        InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {
+        InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
     }
diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs
@@ -164,7 +164,7 @@ pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
 pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
 pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
 pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
-pub use spirv::{SpirvInlineAsmReg, SpirvInlineAsmRegClass};
+pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
 pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
 
 #[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
@@ -179,7 +179,7 @@ pub enum InlineAsmArch {
     Hexagon,
     Mips,
     Mips64,
-    Spirv,
+    SpirV,
 }
 
 impl FromStr for InlineAsmArch {
@@ -197,7 +197,7 @@ impl FromStr for InlineAsmArch {
             "hexagon" => Ok(Self::Hexagon),
             "mips" => Ok(Self::Mips),
             "mips64" => Ok(Self::Mips64),
-            "spirv" => Ok(Self::Spirv),
+            "spirv" => Ok(Self::SpirV),
             _ => Err(()),
         }
     }
@@ -212,7 +212,7 @@ pub enum InlineAsmReg {
     Nvptx(NvptxInlineAsmReg),
     Hexagon(HexagonInlineAsmReg),
     Mips(MipsInlineAsmReg),
-    Spirv(SpirvInlineAsmReg),
+    SpirV(SpirVInlineAsmReg),
 }
 
 impl InlineAsmReg {
@@ -269,8 +269,8 @@ impl InlineAsmReg {
             InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
                 Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
             }
-            InlineAsmArch::Spirv => {
-                Self::Spirv(SpirvInlineAsmReg::parse(arch, has_feature, target, &name)?)
+            InlineAsmArch::SpirV => {
+                Self::SpirV(SpirVInlineAsmReg::parse(arch, has_feature, target, &name)?)
             }
         })
     }
@@ -314,7 +314,7 @@ pub enum InlineAsmRegClass {
     Nvptx(NvptxInlineAsmRegClass),
     Hexagon(HexagonInlineAsmRegClass),
     Mips(MipsInlineAsmRegClass),
-    Spirv(SpirvInlineAsmRegClass),
+    SpirV(SpirVInlineAsmRegClass),
 }
 
 impl InlineAsmRegClass {
@@ -327,7 +327,7 @@ impl InlineAsmRegClass {
             Self::Nvptx(r) => r.name(),
             Self::Hexagon(r) => r.name(),
             Self::Mips(r) => r.name(),
-            Self::Spirv(r) => r.name(),
+            Self::SpirV(r) => r.name(),
         }
     }
 
@@ -343,7 +343,7 @@ impl InlineAsmRegClass {
             Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
             Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
             Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
-            Self::Spirv(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Spirv),
+            Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
         }
     }
 
@@ -366,7 +366,7 @@ impl InlineAsmRegClass {
             Self::Nvptx(r) => r.suggest_modifier(arch, ty),
             Self::Hexagon(r) => r.suggest_modifier(arch, ty),
             Self::Mips(r) => r.suggest_modifier(arch, ty),
-            Self::Spirv(r) => r.suggest_modifier(arch, ty),
+            Self::SpirV(r) => r.suggest_modifier(arch, ty),
         }
     }
 
@@ -385,7 +385,7 @@ impl InlineAsmRegClass {
             Self::Nvptx(r) => r.default_modifier(arch),
             Self::Hexagon(r) => r.default_modifier(arch),
             Self::Mips(r) => r.default_modifier(arch),
-            Self::Spirv(r) => r.default_modifier(arch),
+            Self::SpirV(r) => r.default_modifier(arch),
         }
     }
 
@@ -403,7 +403,7 @@ impl InlineAsmRegClass {
             Self::Nvptx(r) => r.supported_types(arch),
             Self::Hexagon(r) => r.supported_types(arch),
             Self::Mips(r) => r.supported_types(arch),
-            Self::Spirv(r) => r.supported_types(arch),
+            Self::SpirV(r) => r.supported_types(arch),
         }
     }
 
@@ -428,7 +428,7 @@ impl InlineAsmRegClass {
                 InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
                     Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
                 }
-                InlineAsmArch::Spirv => Self::Spirv(SpirvInlineAsmRegClass::parse(arch, name)?),
+                InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
             })
         })
     }
@@ -444,7 +444,7 @@ impl InlineAsmRegClass {
             Self::Nvptx(r) => r.valid_modifiers(arch),
             Self::Hexagon(r) => r.valid_modifiers(arch),
             Self::Mips(r) => r.valid_modifiers(arch),
-            Self::Spirv(r) => r.valid_modifiers(arch),
+            Self::SpirV(r) => r.valid_modifiers(arch),
         }
     }
 }
@@ -587,7 +587,7 @@ pub fn allocatable_registers(
             mips::fill_reg_map(arch, has_feature, target, &mut map);
             map
         }
-        InlineAsmArch::Spirv => {
+        InlineAsmArch::SpirV => {
             let mut map = spirv::regclass_map();
             spirv::fill_reg_map(arch, has_feature, target, &mut map);
             map
diff --git a/compiler/rustc_target/src/asm/spirv.rs b/compiler/rustc_target/src/asm/spirv.rs
@@ -2,12 +2,12 @@ use super::{InlineAsmArch, InlineAsmType};
 use rustc_macros::HashStable_Generic;
 
 def_reg_class! {
-    Spirv SpirvInlineAsmRegClass {
+    SpirV SpirVInlineAsmRegClass {
         reg,
     }
 }
 
-impl SpirvInlineAsmRegClass {
+impl SpirVInlineAsmRegClass {
     pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
         &[]
     }
@@ -42,5 +42,5 @@ impl SpirvInlineAsmRegClass {
 
 def_regs! {
     // SPIR-V is SSA-based, it does not have registers.
-    Spirv SpirvInlineAsmReg SpirvInlineAsmRegClass {}
+    SpirV SpirVInlineAsmReg SpirVInlineAsmRegClass {}
 }

Original file line number	Diff line number	Diff line change
`@@ -260,7 +260,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {`
`260`	`260`	`InlineAsmArch::Nvptx64 => {}`
`261`	`261`	`InlineAsmArch::Hexagon => {}`
`262`	`262`	`InlineAsmArch::Mips \| InlineAsmArch::Mips64 => {}`
`263`		`- InlineAsmArch::Spirv => {}`
	`263`	`+ InlineAsmArch::SpirV => {}`
`264`	`264`	`}`
`265`	`265`	`}`
`266`	`266`	`if !options.contains(InlineAsmOptions::NOMEM) {`
`@@ -519,7 +519,7 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)`
`519`	`519`	`\| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg) => "x",`
`520`	`520`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => "v",`
`521`	`521`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => "^Yk",`
`522`		`- InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {`
	`522`	`+ InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {`
`523`	`523`	`bug!("LLVM backend does not support SPIR-V")`
`524`	`524`	`}`
`525`	`525`	`}`
`@@ -584,7 +584,7 @@ fn modifier_to_llvm(`
`584`	`584`	`_ => unreachable!(),`
`585`	`585`	`},`
`586`	`586`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => None,`
`587`		`- InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {`
	`587`	`+ InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {`
`588`	`588`	`bug!("LLVM backend does not support SPIR-V")`
`589`	`589`	`}`
`590`	`590`	`}`
`@@ -626,7 +626,7 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll`
`626`	`626`	`\| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)`
`627`	`627`	`\| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => cx.type_f32(),`
`628`	`628`	`InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => cx.type_i16(),`
`629`		`- InlineAsmRegClass::Spirv(SpirvInlineAsmRegClass::reg) => {`
	`629`	`+ InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {`
`630`	`630`	`bug!("LLVM backend does not support SPIR-V")`
`631`	`631`	`}`
`632`	`632`	`}`
Original file line number	Diff line number	Diff line change
`@@ -164,7 +164,7 @@ pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};`
`164`	`164`	`pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};`
`165`	`165`	`pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};`
`166`	`166`	`pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};`
`167`		`-pub use spirv::{SpirvInlineAsmReg, SpirvInlineAsmRegClass};`
	`167`	`+pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};`
`168`	`168`	`pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};`
`169`	`169`
`170`	`170`	`#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]`
`@@ -179,7 +179,7 @@ pub enum InlineAsmArch {`
`179`	`179`	`Hexagon,`
`180`	`180`	`Mips,`
`181`	`181`	`Mips64,`
`182`		`- Spirv,`
	`182`	`+ SpirV,`
`183`	`183`	`}`
`184`	`184`
`185`	`185`	`impl FromStr for InlineAsmArch {`
`@@ -197,7 +197,7 @@ impl FromStr for InlineAsmArch {`
`197`	`197`	`"hexagon" => Ok(Self::Hexagon),`
`198`	`198`	`"mips" => Ok(Self::Mips),`
`199`	`199`	`"mips64" => Ok(Self::Mips64),`
`200`		`- "spirv" => Ok(Self::Spirv),`
	`200`	`+ "spirv" => Ok(Self::SpirV),`
`201`	`201`	`_ => Err(()),`
`202`	`202`	`}`
`203`	`203`	`}`
`@@ -212,7 +212,7 @@ pub enum InlineAsmReg {`
`212`	`212`	`Nvptx(NvptxInlineAsmReg),`
`213`	`213`	`Hexagon(HexagonInlineAsmReg),`
`214`	`214`	`Mips(MipsInlineAsmReg),`
`215`		`- Spirv(SpirvInlineAsmReg),`
	`215`	`+ SpirV(SpirVInlineAsmReg),`
`216`	`216`	`}`
`217`	`217`
`218`	`218`	`impl InlineAsmReg {`
`@@ -269,8 +269,8 @@ impl InlineAsmReg {`
`269`	`269`	`InlineAsmArch::Mips \| InlineAsmArch::Mips64 => {`
`270`	`270`	`Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)`
`271`	`271`	`}`
`272`		`- InlineAsmArch::Spirv => {`
`273`		`- Self::Spirv(SpirvInlineAsmReg::parse(arch, has_feature, target, &name)?)`
	`272`	`+ InlineAsmArch::SpirV => {`
	`273`	`+ Self::SpirV(SpirVInlineAsmReg::parse(arch, has_feature, target, &name)?)`
`274`	`274`	`}`
`275`	`275`	`})`
`276`	`276`	`}`
`@@ -314,7 +314,7 @@ pub enum InlineAsmRegClass {`
`314`	`314`	`Nvptx(NvptxInlineAsmRegClass),`
`315`	`315`	`Hexagon(HexagonInlineAsmRegClass),`
`316`	`316`	`Mips(MipsInlineAsmRegClass),`
`317`		`- Spirv(SpirvInlineAsmRegClass),`
	`317`	`+ SpirV(SpirVInlineAsmRegClass),`
`318`	`318`	`}`
`319`	`319`
`320`	`320`	`impl InlineAsmRegClass {`
`@@ -327,7 +327,7 @@ impl InlineAsmRegClass {`
`327`	`327`	`Self::Nvptx(r) => r.name(),`
`328`	`328`	`Self::Hexagon(r) => r.name(),`
`329`	`329`	`Self::Mips(r) => r.name(),`
`330`		`- Self::Spirv(r) => r.name(),`
	`330`	`+ Self::SpirV(r) => r.name(),`
`331`	`331`	`}`
`332`	`332`	`}`
`333`	`333`
`@@ -343,7 +343,7 @@ impl InlineAsmRegClass {`
`343`	`343`	`Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),`
`344`	`344`	`Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),`
`345`	`345`	`Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),`
`346`		`- Self::Spirv(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Spirv),`
	`346`	`+ Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),`
`347`	`347`	`}`
`348`	`348`	`}`
`349`	`349`
`@@ -366,7 +366,7 @@ impl InlineAsmRegClass {`
`366`	`366`	`Self::Nvptx(r) => r.suggest_modifier(arch, ty),`
`367`	`367`	`Self::Hexagon(r) => r.suggest_modifier(arch, ty),`
`368`	`368`	`Self::Mips(r) => r.suggest_modifier(arch, ty),`
`369`		`- Self::Spirv(r) => r.suggest_modifier(arch, ty),`
	`369`	`+ Self::SpirV(r) => r.suggest_modifier(arch, ty),`
`370`	`370`	`}`
`371`	`371`	`}`
`372`	`372`
`@@ -385,7 +385,7 @@ impl InlineAsmRegClass {`
`385`	`385`	`Self::Nvptx(r) => r.default_modifier(arch),`
`386`	`386`	`Self::Hexagon(r) => r.default_modifier(arch),`
`387`	`387`	`Self::Mips(r) => r.default_modifier(arch),`
`388`		`- Self::Spirv(r) => r.default_modifier(arch),`
	`388`	`+ Self::SpirV(r) => r.default_modifier(arch),`
`389`	`389`	`}`
`390`	`390`	`}`
`391`	`391`
`@@ -403,7 +403,7 @@ impl InlineAsmRegClass {`
`403`	`403`	`Self::Nvptx(r) => r.supported_types(arch),`
`404`	`404`	`Self::Hexagon(r) => r.supported_types(arch),`
`405`	`405`	`Self::Mips(r) => r.supported_types(arch),`
`406`		`- Self::Spirv(r) => r.supported_types(arch),`
	`406`	`+ Self::SpirV(r) => r.supported_types(arch),`
`407`	`407`	`}`
`408`	`408`	`}`
`409`	`409`
`@@ -428,7 +428,7 @@ impl InlineAsmRegClass {`
`428`	`428`	`InlineAsmArch::Mips \| InlineAsmArch::Mips64 => {`
`429`	`429`	`Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)`
`430`	`430`	`}`
`431`		`- InlineAsmArch::Spirv => Self::Spirv(SpirvInlineAsmRegClass::parse(arch, name)?),`
	`431`	`+ InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),`
`432`	`432`	`})`
`433`	`433`	`})`
`434`	`434`	`}`
`@@ -444,7 +444,7 @@ impl InlineAsmRegClass {`
`444`	`444`	`Self::Nvptx(r) => r.valid_modifiers(arch),`
`445`	`445`	`Self::Hexagon(r) => r.valid_modifiers(arch),`
`446`	`446`	`Self::Mips(r) => r.valid_modifiers(arch),`
`447`		`- Self::Spirv(r) => r.valid_modifiers(arch),`
	`447`	`+ Self::SpirV(r) => r.valid_modifiers(arch),`
`448`	`448`	`}`
`449`	`449`	`}`
`450`	`450`	`}`
`@@ -587,7 +587,7 @@ pub fn allocatable_registers(`
`587`	`587`	`mips::fill_reg_map(arch, has_feature, target, &mut map);`
`588`	`588`	`map`
`589`	`589`	`}`
`590`		`- InlineAsmArch::Spirv => {`
	`590`	`+ InlineAsmArch::SpirV => {`
`591`	`591`	`let mut map = spirv::regclass_map();`
`592`	`592`	`spirv::fill_reg_map(arch, has_feature, target, &mut map);`
`593`	`593`	`map`
Original file line number	Diff line number	Diff line change
`@@ -2,12 +2,12 @@ use super::{InlineAsmArch, InlineAsmType};`
`2`	`2`	`use rustc_macros::HashStable_Generic;`
`3`	`3`
`4`	`4`	`def_reg_class! {`
`5`		`- Spirv SpirvInlineAsmRegClass {`
	`5`	`+ SpirV SpirVInlineAsmRegClass {`
`6`	`6`	`reg,`
`7`	`7`	`}`
`8`	`8`	`}`
`9`	`9`
`10`		`-impl SpirvInlineAsmRegClass {`
	`10`	`+impl SpirVInlineAsmRegClass {`
`11`	`11`	`pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {`
`12`	`12`	`&[]`
`13`	`13`	`}`
`@@ -42,5 +42,5 @@ impl SpirvInlineAsmRegClass {`
`42`	`42`
`43`	`43`	`def_regs! {`
`44`	`44`	`// SPIR-V is SSA-based, it does not have registers.`
`45`		`- Spirv SpirvInlineAsmReg SpirvInlineAsmRegClass {}`
	`45`	`+ SpirV SpirVInlineAsmReg SpirVInlineAsmRegClass {}`
`46`	`46`	`}`